Speculative and Predicated Execution Support for Instruction-Level Parallel Processing

Hwu 推测执行和断言执行是VLIW和超标量处理器并行性的两个重要来源。 推测执行在知道指令需要执行之前尝试性地执行指令。 谓词执行将多个可能的执行路径合并为单个路径，以便硬件可以同时处理多个路径。 这两种方法都允许编译器在存在条件分支的情况下提取程序并行性。 随着超标量和VLIW设计在微处理器工业中变得越来越流行，这些方法对于未来的高性能微处理器实现其性能目标变得越来越重要。 本计画针对未来超标量与VLIW微处理器系统整合推测执行与预测执行所涉及的三个关键问题。 首先，正在研究增加对推测执行和断言执行的架构支持级别的设计复杂性。 其次，正在开发利用每个层次的体系结构支持的编译器优化器和编译器。 第三，一个综合的方法被定义为协调推测执行和谓词执行，以最好地提高程序执行性能。 其目标是提供微处理器行业所需的架构专业知识和编译器原型，以了解每一级硬件支持的成本和有效性。

Hwu Speculative execution and predicated execution are two important sources of parallelism for VLIW and superscalar processors. Speculative execution tentatively executes instructions before knowing that their execution is required. Predicated execution merges multiple possible execution paths into a single path so that the hardware can simultaneously process multiple paths. Both methods allow the compiler to extract program parallelism in the presence of conditional branches. With superscalar and VLIW designs becoming increasingly popular in the microprocessor industry, these methods have become increasingly important for future high performance microprocessors to achieve their performance goals. This project addresses three critical issues involved in incorporating speculative execution and predicated execution into future superscalar and VLIW microprocessor systems. First, the design complexity of increasing levels of architecture support for speculative execution and predicated execution are being studied. Secondly, compiler optimizers and schedulers that exploit each level of the architecture support are being developed. Thirdly, an integrated approach is being defined to coordinate speculative execution and predicated execution to best improve program execution performance. The objective is to provide architecture expertise and compiler prototypes required for the microprocessor industry to understand the cost and effectiveness of each level of hardware support.