Architecture, Algorithms and Software in the Design of a Massively Parallel, Fine Grain Processor

这个项目正在调查一系列大规模并行计算机的设计、实现和使用，这些计算机每位使用一个处理器。在早期项目中完成的第一代设计，在一块电路板上包含16,384个细粒处理器。处理器包含少量并行逻辑电路和控制逻辑和互连的配置存储器。通过设置所有配置寄存器，将整台机器转换为解决问题的专用计算机，从而对整台机器进行编程。通过提高芯片上处理器的密度以及互连和接口的速度，该项目将机器的运转率提高了4%到10%。除了设计和实现体系结构外，该项目还开发了机器的高级和低级编程工具。最后，在这些机器上解决计算密集型问题的算法正在开发和测试中。

This project is investigating the design, implementation, and use of a family of family of massively parallel computers that use one processor per digit. A first generation design, completed in an earlier project, contains 16,384 fine grain processors on a single board. The processors contain a small number of parallel logic circuits and a configuration memory that controls the logic and interconnect. The entire machine is programmed for a problem by setting all configuration registers to transform the machine into a special-purpose computer for the problem. By improving the density of processors on chips and the speeds of interconnect and interface, this project is increasing the operation rate of the machine by a factor of 4 to 10. In addition to the design and implementation of architectures, this project is developing both high and low level programming tools for the machines. Finally, algorithms for solving compute intensive problems on these machines are being developed and tested.