Atomic-Scale Mechanism of Metal Etching Reactions Determined by High-Speed Variable-Temperature Scanning Tunneling Microscopy

利用高速变温STM和宏观表面分析技术研究金属蚀刻反应的机理。由于对使用铜作为集成电路中的互连材料感兴趣，该项目将侧重于铜的卤素蚀刻。研究将集中在卤素蚀刻铜的两个主要反应步骤：1)形成卤化铜和2)升华和/或反应去除卤化物。限制蚀刻速率的因素将通过STM“电影”在蚀刻条件下监测表面直接确定。基于STM观察到的基本反应步骤，建立了一个机械动力学模型。结果将指导新的蚀刻工艺和新的蚀刻方案的发展，以直接绘制精细金属线条。这项研究有望提供对蚀刻反应的原子级理解，这是集成电路制造的重要一步。这种理解将有助于开发新的蚀刻工艺，使新材料能够用于集成电路。在下个世纪，将需要使用新材料来继续提高设备速度和减小设备尺寸的趋势。这项研究的结果将对用于计算、信息处理和远程通信的先进设备和集成电路的制造和一般性能产生影响。＊＊＊

94114404 Altman The mechanism of metal etching reactions will be studied using high speed variable temperature STM along with macroscopic surface analysis techniques. The project will focus on halogen etching of copper because of interest in using copper as an interconnect material in integrated circuits. The study will concentrate on the two major reaction steps in halogen etching of copper: 1)copper halide formation and 2)halide removal by sublimation and/or reaction. The factors that limit etching rates will be directly determined through STM "movies" monitoring the surface under etching conditions. A mechanistic kinetic model based on the elementary reaction steps observed with STM will be developed. The results will guide development of new etching processes and new etching schemes to directly pattern fine metal lines. %%% This research is anticipated to provide an atomic-level understanding of etching reactions that are an important step in integrated circuit fabrication. This understanding will aid development of new etching processes to allow new materials to be used in integrated circuits. The use of new materials will be required to continue the trend of increased device speed and decreased device size into the next century. The results of this research will have an impact on the fabrication and general perform ance of advanced devices and integrated circuits used in computing, information processing, and tele communica tions. ***