CAREER: Improving Compiler/Architecture Synergy

*9734023泰森这个项目探索了编译过程中执行的代码转换和指令集设计之间的交互作用。指令集设计中的几项修改正在调查中，每一项修改都试图通过增加在运行时传输到硬件的编译时间信息量来提高处理器的整体性能。一些修改，例如概率预取或分支表索引，相当于可以提高性能的提示，而不需要体系结构的所有实现使用该信息。其他方法，如在一个或多个寄存器标识符上施加FIFO语义，使编译器能够调度资源，并要求所有实现都符合调度。每一项修改都将使用研究生课程的课堂项目和研究生的个人研究来探索。这个项目产生的模拟和其他工具将被引入到本科课程中。***

*** 9734023 Tyson This project explores the interaction between code transformation performed during compilation and instruction set design. Several modifications in instruction set design are under investigation, each of which attempts to improve overall processor performance by increasing the amount of compile time information transmitted to the hardware at runtime. Some modifications, such as probabilistic prefetch or branch table indexing, amount to hints that may improve performance without requiring all implementations of an architecture to use the information. Others, such as imposition of FIFO semantics on one or more register identifiers, enable compilers to schedule resources and require that all implementations comply with the scheduling. Each of the modifications will be explored using both classroom projects for graduate courses and individual research by graduate students. Simulation and other tools arising from this project will be introduced into the undergraduate curriculum. ***