Computational Methods for the Simulation of Chemical Vapor Deposition on Rough Surfaces

DMS 9805547 马蒂亚斯·K戈贝尔 粗糙表面化学气相沉积模拟的计算方法 摘要： 在化学气相沉积（CVD）工艺中，将反应气体的混合物施加到化学反应器的反应室中的半导体晶片的表面。通过与表面材料的表面反应在表面上形成材料薄膜。 晶片表面包含小的沟槽和孔，统称为特征，用于互连线、晶体管栅极等，从而使表面粗糙。目前，基于Navier-Stokes方程的反应器比例模型（RSM）捕获整个反应器室中的反应气体的流动，其典型尺寸为10厘米，并且基于动力学方程的特征比例模型（FSM）预测单个特征内的膜生长轮廓，其典型尺寸为1微米。由于长度尺度的极端差异，最好通过引入典型尺寸为1毫米量级的介观尺度模型（MSM）来获得跨越所有感兴趣的长度尺度的集成过程模型。 本计画将发展此尺度之低压区适当动力学方程式之数学模式与计算方法。 该项目是计算机芯片制造过程建模工作的一部分。计算机已经并将继续是我们经济和技术的最重要工具之一。有一种趋势是生产更小数量的更专业的计算机芯片，例如用于空间探索或防御系统中的特定应用。 但是，测试制造过程所需的原型运行使用昂贵的化学品，并产生有害的废气，这些废气在释放到环境中之前需要进行处理。 由于这些原因，对从单个设备到工厂地板的所有尺度上的制造过程进行模拟的兴趣一直在增加。该项目将有助于为计算机芯片的关键生产步骤之一化学气相沉积过程开发适当的模型和更好的数值技术。在这个过程中，沉积一层薄薄的材料，形成电线或电子设备，构成最终产品中的计算机芯片。

DMS 9805547 Matthias K. Gobbert Computational Methods for the Simulation of Chemical Vapor Deposition on Rough Surfaces Abstract: In chemical vapor deposition (CVD) processes a mixture of reacting gases is applied to the surface of a semiconductor wafer in the reaction chamber of a chemical reactor. A thin film of material is formed on the surface via surface reactions with the surface material. The wafer surface contains small trenches and holes, collectively referred to as features, for interconnect lines, transistor gates, etc., thus making the surface rough. Currently, reactor scale models (RSM) based on the Navier-Stokes equations capture the flow of the reacting gases throughout the entire reactor chamber with a typical dimension of 10 centimeters, and feature scale models (FSM) based on kinetic equations predict the film growth profile inside a single feature with a typical dimension of 1 micrometer. Due to the extreme difference of length scales, an integrated process model spanning all length scales of interest is best obtained by introducing a mesoscopic scale model (MSM) with typical dimension on the order of 1 millimeter. This project will develop the mathematical model and computational methods for the appropriate kinetic equations in the low pressure regime on this scale. This project is part of an effort at modeling the manufacturing processes of computer chips. Computers are already and will continue to be one of the most important tools of our economy and technology. There is a trend towards more specialized computer chips to be produced in smaller numbers, for instance for specific applications in space exploration or defense systems. But prototype runs necessary to test the manufacturing processes use expensive chemicals and produce hazardous exhaust gases, which need to be treated before releasing them to the environment. For these reasons, interest in simulating the manufacturing processes on all scales from individual device to fa ctory floor has been increasing. This project will contribute to the development of appropriate models as well as better numerical techniques for the process of chemical vapor deposition, one of the crucial production steps for computer chips. In this process, a thin layer of material is deposited to form either the electrical lines or the electronic devices that make up the computer chip in the final product.