Datapath Design and Code Generation for VLIW ASIPs

超大指令字(VLIW)专用指令集处理器(ASIP)内核实现了性能/功率/能量的折衷，这在竞争异常激烈的嵌入式多媒体和信号处理市场中非常有吸引力。具体地说，与基于集中式寄存器堆的数据路径相比，包括具有相关联(本地)寄存器堆的功能单元集群的专用数据路径可以实现显著的性能/功率/能量增益。然而，这种专门的数据路径带来了重大的研究和实践挑战。这项研究的重点是：(1)VLIW ASIP数据路径的综合；(2)为此类专用处理器开发高质量的可重定向编译器。该方法包括一个新的阶段化/分解问题，它首先考虑了操作和数据对象与专用数据路径的功能单元和寄存器堆的联合绑定。将开发互补的主动优化启发式算法，以执行依赖于数据路径的代码转换，利用问题对称性来显著减少搜索空间，并有效地绑定/分配和调度操作、数据对象和数据传输到数据路径的资源上。如果这项研究成功，它将有助于提供越来越多的技术，为嵌入式系统行业提供竞争优势。

Very Large Instruction Word (VLIW) Application Specific Instruction-Set Processor (ASIP) cores realize performance/power/energy tradeoffs that can be very attractive in the exceedingly competitive embedded multimedia and signal processing market. In particular, specialized datapaths comprising clusters of functional units with associated (local) register files can enable significant performance/power/energy gains over those based on centralized register files. However, such specialized datapaths pose significant research and practical challenges. The proposed research focuses on jointly addressing (1) the synthesis of VLIW ASIP datapaths, and (2) the development of high-quality retargetable compilers for such specialized processors. The proposed methodology includes a novel problem phasing/decomposition that first considers the joint binding of operations and data objects to the functional units and register files of the specialized datapath. Complementary aggressive optimization heuristics will be developed to perform datapath dependent code transformations, exploit problem symmetries to dramatically reduce the search space, and to effectively bind/assign and schedule operations, data objects and data transfers onto the datapath's resources. If this research is successful, it will contribute to technologies that will increasingly provide the competitive edgefor the embedded systems industry.