CISE Next Generation Software: Software Systems: Compiling for Speculative Distributed Microarchitectures

这个项目引入了一种新的编译器范例，称为无保守假设编译，它打破了保守编译时假设的障碍，这是当前一代编译器最严重的限制之一。新范式是由新兴的推测性分布式微架构实现的。在提议的项目中，pi将为这种架构实现一个完整的编译器系统。这项工作将补充已经在进行中的Purdue Multiplex架构项目，该项目正在由相同的pi进行调查。普渡Multiplex结合了芯片上集成的趋势和积极的推测指令执行。它的分布式、单芯片微架构将传统的多处理器线程级并行性与当今激进的超标量处理器的推测执行集成在一起。编译器从顺序程序生成线程，这些线程不一定是独立的，硬件通过推测和回滚机制保证线程间控制/数据依赖的正确性。通过提供对线程级推测的支持，硬件减轻了编译器保证线程间独立性的负担，从而实现了我们保守的无假设编译范例。我们的编译器将通过新的分析和新颖的转换推测性地并行化非数值应用程序的未开发领域。我们的编译器将紧密集成技术，以利用指令级和线程级并行性。

EIA-9974976Purdue UniversityEigenmann, RudolfCompiling for Speculative Distributed MicroarchitecturesThis project introduces a novel compiler paradigm called conservative-assumption-free compilation, which breaks the barrier of a conservative compile-time assumption, one of the most severe limitations of current generation of compilers. The new paradigm is enabled by emerging speculative, distributed microarchitechtures. In the proposed project the PIs will implement a full compiler system for such architectures. The effort will complement the already-onging Purdue Multiplex architecture project being investigated by the same PIs.Purdue Multiplex combines trends of increasing on-chip integration with aggressive speculative instruction execution. Its distributed, single-chip microarchitecture integrates conventional multiprocessor thread-level parallelism with speculative execution of today's aggressive superscalar processors. The compiler generates threads, which are not necessarily independent, from a sequential program and the hardware guarantees correctness in case of inter-thread control/data dependencies via speculation and rollback mechanisms. By providing support for thread-level speculation, the hardware relieves the compiler of the burden of guaranteeing inter-thread independence, enabling our conservative-assumption-free compilation paradigm. Our compiler will speculatively parallelize the unexplored domain of non-numeric applications via new analyses and novel transformations. Our compiler will tightly integrate techniques to exploit both instruction-level and thread-level parallelism.