Acquisition of a Chemical Mechanical Polishing (CMP) System to Provide Planarization Capability within the Advanced Thin Film Devices Prototyping Facility at Carnegie Mellon U
Acquisition of a Chemical Mechanical Polishing (CMP) System to Provide Planarization Capability within the Advanced Thin Film Devices Prototyping Facility at Carnegie Mellon U
批准号:
9977679
负责人:
James Bain
金额:
$14.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
1999
资助国家:
美国
项目状态:
已结题
起止时间:
1999-09-01 至 2001-08-31
中文摘要
这项拨款将增加一个基本的新的薄膜加工能力,即化学机械抛光,或CMP,现有的薄膜器件制造能力在卡内基梅隆大学的洁净室。 具体来说,它将增加一个Strasbaugh 6EC实验室平面化工具,一个交钥匙CMP系统,和行业标准。在卡内基梅隆大学的洁净室,这种工艺能力将应用于磁性薄膜器件的制造,特别是记录磁头。 CMP工艺还将应用于磁性薄膜器件与CMU开发的CMOS MEMS(互补金属氧化物半导体微机电系统)器件工艺的集成。CMOS MEMS技术与磁性器件的集成被视为高度集成计算系统开发中的重要一步,该高度集成计算系统将大量非易失性存储器与高速计算能力集成在一起。CMU开发的CMOS MEMS工艺允许机械和磁性器件与包含在底层中的有源电路紧密集成。在完整的CMOS晶圆上构建精细的磁性和机械几何结构需要平坦化CMOS层的形貌。这允许光刻工具的所需焦深以及用于图案化磁性和机械器件的光刻胶层的厚度最小化。*
英文摘要
9977679BainThis grant will add a fundamental new thin film processing capability, namely chemical-mechanical polishing, or CMP, to the existing thin film device fabrication capability within the clean-room of Carnegie Mellon University. Specifically it will add a Strasbaugh 6EC laboratory planarization tool, a turnkey CMP system, and industry standard.Within the Carnegie Mellon clean-room, this process capability will be applied to the making of magnetic thin film devices, specifically recording heads. The CMP process will also be applied to the integration of magnetic thin film devices with the CMOS MEMS (Complimentary Metal Oxide Semiconductor Micro-Electro-Mechanical Systems) device process that has been developed at CMU. The integration of the CMOS MEMS technology with magnetic devices is seen as an important step in the development of highly integrated computing systems that integrate massive amounts of nonvolatile storage with high speed computation capability. The CMOS MEMS process developed at CMU allows mechanical and magnetic devices to be closely integrated with active circuits, which are contained in the underlying layers. Constructing fine magnetic and mechanical geometries on top of a complete CMOS wafer requires that the topography of the CMOS layers be planadze& This allows the required depth of focus of the lithographic tool, and the thickness of the photoresist layers used to pattern the magnetic and mechanical devices to be minimized.***
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