ITR: Adaptive Fault Recovery for Networked Digital Systems

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In this project an integrated fault recovery system is developed thatquickly isolates faults in programmable digital components anddetermines new device programming configurations to return themto full functionality. After detection of a hardware fault in a digitalcomponent such as a digital signal processor or a field-programmablegate array, an attempt to recover from the fault is made at the local embedded system affected by the fault. If the local system is unable to complete the recovery effort, a computational-superior remote systemmay be accessed via a local network to aid in the recovery effort.In either case, the result of the recovery procedure is a new deviceconfiguration (instruction sequence or configuration bitstream). This configuration allows the affected system to perform the same logical function as the original configuration while avoiding the detected functional hardware fault.The direct result of this work is a set of compilation techniques forboth DSPs and FPGAs that produce instruction and bitstreamconfigurations that avoid detected hardware faults.These tools are directly integrated into a networkedenvironment through the use of TCP/IP transfer mechanisms built intooperating systems frequently used for scientific computing.