Research for Mixed Signal Electronic Technologies: A Joint Initiative Between NSF and SRC: Fast Methods of Coupled EM. Circuit and Logic Simulation for Giga-Scale

该项目旨在开发用于快速模拟千兆级片上系统的快速算法，其中耦合电路，逻辑和电磁（EM）效应（包括RLC寄生，耦合，串扰，集肤和热效应-包括准静态和全波）变得越来越重要。对于耦合的电磁和电路仿真，我们提出了一种新的部分元件等效电路（PEEC）方法。对于耦合电磁和数字仿真，我们建议在电磁分析中研究变时间步进，并使用与数字事件的保守同步。更具体地说，我们的方法包括以下关键要素：开发基于积分方程的快速解决方法，使这些设置中的电磁仿真可行，并允许在不同程度的模型复杂程度下进行分层或多层电磁分析。通过部分等效电路方法的一种变化实现快速和分层的三角网格镶嵌方案。将电磁仿真方案与数字逻辑仿真直接耦合，以分析电源-地平面情况下的开关和地弹跳。利用EM、电路级和耦合系统矩阵中存在的结构和冗余，以大幅减少内存和计算时间，使严格和完整的耦合模拟对复杂的片上系统是可行的。此外，还针对灵敏度分析、降阶建模和多物理场仿真进行了研究。开发了用于电路仿真的常微分方程（ODE）代码生成的优化编译技术，以及用于快速分层电路/电磁仿真的利用电路结构规则的优化编译技术。测试所提出的耦合EM/电路和EM/数字仿真的应用驱动程序将包括(1)芯片上的千兆赫CMOS收发器，以及(2)千兆赫数字电路的电源/地网络，包括门开关活动建模。快速和严格的EM/电路和EM/逻辑仿真的发展将实现下一代混合信号电路和系统的准确而有效的签名仿真，实现环路设计优化和架构权衡的仿真，并最终实现EM效应难以表征，预测和测量的可测试性设计。

This project aims at developing fast algorithms for rapid simulation of giga-scale systems-on-chip, where coupled circuit, logic, and electromagnetic (EM) effects (including RLC parasitics, coupling, cross talk, skin and thermal effects---both quasi-static and full-wave), are becoming increasingly important. For coupled EM and circuit simulation, we propose to investigate a novel partial-element equivalent electric circuit (PEEC) approach. For coupled EM and digital simulation, we propose to investigate variant time stepping in EM analysis and to use conservative synchronization with digital events. More specifically, our approach consists of the following key elements:Developing fast integral-equation-based solution methods that will make feasible EM simulation in these settings, and will permit hierarchical or multilevel EM analyses at varying degrees of model complexity.Implementation of fast and hierarchical schemes through a variation of the partial equivalent electric circuit method for triangular mesh tessellations.Coupling of EM simulation schemes directly to digital logic simulation in order to analyze switching and ground bounce in power-ground plane situations.Exploitation of structure and redundancies present in EM, circuit-level as well as coupled-system matrices in order to drastically reduce memory and computation time to a degree such that rigorous and complete coupled simulation will be feasible for complex-systems-on-chip. Sensitivity analysis, reduced-order modeling, and multi-physics simulations are targeted in addition.Development of optimized compilation techniques for generating ordinary differential equation (ODE) code for circuit simulation, and for exploiting the circuit structural regularity for fast hierarchical circuit/EM simulation. The application drivers for testing proposed coupled EM/circuit and EM/digital simulation will include (1) Giga-hertz CMOS transceivers on chip, and (2) Power/ground network of giga-hertz digital circuits including gate switching activity modeling.It is intended that the development of fast and rigorous EM/circuit and EM/logic simulation will enable accurate yet efficient sign-off simulation of next generation mixed-signal circuits and systems, enable simulation in the loop design optimization and architecture tradeoff, and finally enable design for testability where EM effects are becoming hard to characterize, predict, and measure.