Ultra High Performance Digital Circuit Design and Synthesis

本提案的重点是极高的性能（非常高的速度，但也节能）的数字IC设计。提出的研究有三个任务：1)高性能数字逻辑技术；2)CAD工具开发以帮助快速部署高性能逻辑技术；3)高性能逻辑技术的应用；任务1：高性能数字逻辑技术的研究：重点是最大限度地提高输出预测逻辑（OPL）技术的性能，并开发更快和/或更节能的逻辑技术。任务2：快速实现高性能数字逻辑的CAD：技术根据本提案，将开发两种CAD工具来简化OPL电路的设计和验证：1)OPL电路的静态时序分析工具，以及2)OPL电路的自动晶体管/栅极尺寸工具，以最大限度地减少延迟目标下的能耗。此外，一个强大的基于凸优化的工具，用于自动晶体管和栅极尺寸的OPL电路正在研究。该工具将最大限度地减少能源消耗，同时达到指定的延迟目标。任务3：高性能数字逻辑技术的应用研究：应用包括：1)一种新的64b加法器架构，具有模拟的最坏情况延迟（在严重的工艺、电压和温度变化下）3.3扇出4逆变器延迟。2)一个非常快的浮点分频器，对于0.20微米的TSMC工艺，延迟可能为6ns。该分频器将在0.20微米制程中以至少3ghz的频率运行，从而首次在信号处理和通信电路中使用分频。3)一种新的FPGA架构，称为OPL-FPGA，这表明FPGA可以接近标准单元asic所获得的电路速度。将通用数据路径电路映射到该架构进一步表明，与最先进的商用fpga相比，至少可以实现3.3倍的加速。

The focus of this proposal is on extremely high performance (very high speed, but also energy efficient) digital IC design. The proposed research has three tasks: 1) high performance digital logic techniques, 2) CAD tool development to aid rapid deployment of the high performance logic techniques, and 3) applications of the high performance logic techniques; in particular, the design of circuit blocks that demonstrate unprecedented speed, while still having reasonable energy efficiencyTask 1: Research on High Performance Digital Logic Techniques: Focus is on maximizing the performance of the output prediction logic (OPL) technique, and developing yet faster and/or more energy efficient logic techniques.Task 2: CAD for Rapid Implementation of High Performance Digital Logic:TechniquesTwo CAD tools will be developed to ease design and verification of OPL circuits under this proposal: 1) A static timing analysis tool for OPL circuits, and 2) an automatic transistor/gate sizing tool for OPL circuits that minimizes energy consumption subject to delay goals. Also a powerful convex-optimization-based tool for automatic transistor and gate sizing for OPL circuits is being investigated. The tool will minimize energy consumption while achieving a specified delay target.Task 3: Research on Applications of High Performance Digital LogicTechniques:Applications include: 1) a new 64b adder architecture having a simulated worst-casedelay (under severe process, voltage and temperature variations) of 3.3fanout-of-four inverter delays. 2) a very fast floating-point divider with the possibility of a latency of 6ns for a 0.20-micron TSMC process. This divider will run at a frequency of at least 3 GHz in this 0.20-micron process, enabling the use of division for the very first time in signal processing and communications circuits. 3) a new FPGA architecture, called OPL-FPGA, which suggests an FPGA could approach the circuit speeds obtained by standard cell ASICs. Mapping common datapath circuits to this architecture further suggests that speedups of at least 3.3X over state-of-the-art commercial FPGAs are attainable.