Ultra High Speed Digital Circuit Synthesis and Layout

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The synthesis and layout of control (random) logic blocks for future 1 GHzand beyond clock frequencies will be a major bottleneck in future digitalsystem design. The research that is proposed here exactly addresses thisproblem by seeking to determine how to synthesize and layout the absolutefastest possible transistor-based implementations of control logicnetworks. It focuses on enabling each step in the design automation flow tofind circuit implementations of maximum possible speed. In particular, whatis being examined carefully is the choice of logic family, the degree andtype of logic minimization, new technology mapping algorithms, and newlayout strategies that make control logic network layouts look similar todatapath layouts. The primary outcome of this research will be a completedesign automation flow consisting of a suite of optimized and efficientcomputer-aided design tools, and an optimized Clock-Delayed domino logicfamily that together will synthesize and layout extremely reliable,mainstream control logic block implementations that are two to three timesfaster than what is possible with static CMOS.