Ultra High Speed Digital Circuit Synthesis and Layout

超高速数字电路综合与布局

• 批准号: 9901166
• 负责人: Carl Sechen
• 金额: $ 25.27万
• 依托单位: University of Washington
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1999
• 资助国家: 美国
• 起止时间: 1999-09-01 至 2003-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9901166&HistoricalAwards=false
• 关键词: Ultra; Speed; Digital; Circuit; Synthesis

The synthesis and layout of control (random) logic blocks for future 1 GHzand beyond clock frequencies will be a major bottleneck in future digitalsystem design. The research that is proposed here exactly addresses thisproblem by seeking to determine how to synthesize and layout the absolutefastest possible transistor-based implementations of control logicnetworks. It focuses on enabling each step in the design automation flow tofind circuit implementations of maximum possible speed. In particular, whatis being examined carefully is the choice of logic family, the degree andtype of logic minimization, new technology mapping algorithms, and newlayout strategies that make control logic network layouts look similar todatapath layouts. The primary outcome of this research will be a completedesign automation flow consisting of a suite of optimized and efficientcomputer-aided design tools, and an optimized Clock-Delayed domino logicfamily that together will synthesize and layout extremely reliable,mainstream control logic block implementations that are two to three timesfaster than what is possible with static CMOS.

未来1GHz及更高时钟频率的控制（随机）逻辑块的综合和布局将成为未来数字系统设计的主要瓶颈。这里提出的研究正是通过寻求确定如何合成和布局绝对最快的基于晶体管的控制逻辑网络实现来解决这个问题。它的重点是使设计自动化流程中的每一步都能找到最大可能速度的电路实现。特别是，正在仔细研究的是逻辑家族的选择，逻辑最小化的程度和类型，新的技术映射算法，以及使控制逻辑网络布局看起来类似于数据路径布局的新布局策略。这项研究的主要成果将是一个完整的设计自动化流程，包括一套优化和高效的计算机辅助设计工具，以及一个优化的时钟延迟多米诺逻辑家族，它们将共同合成和布局非常可靠的主流控制逻辑块实现，比静态CMOS快两到三倍。