Collaborative Research: Low Power CMOS Circuits and Systems for Next Generation Wireless Information Technology

在各种各样的信息技术产品中嵌入无线功能的趋势正在迅速增长；最近以单片形式出现的收发器，将来可能以片上集成为主的产品功能。这些设备必须具有低功耗，以满足电池保护和热考虑。在拥挤的射频（RF）频谱中，良好的接收器灵敏度和信号处理也是必不可少的；然而，这一要求与低功耗电路设计相冲突。我们建议开发低功耗CMOS电路，以改善功耗和射频性能之间的权衡。当前CMOS低噪声放大器（LNA）的噪声系数低至0.8 dB，输入截距点高达+18dBm，功率低至1.5 mW；但是，这些规格不能同时获得。同样，CMOS混频器可以满足要求严格的CDMA通信标准的线性度和噪声系数，但只有在高功率成本。为了解决这些问题，我们提出了一些策略：(a)在给定性能水平下降低功耗，以及(b)允许功率与射频性能的动态权衡。这些策略包括：(1)通过反射安排在两个不同频率上重复使用放大器级，从而减少接收器所需的高性能、高电流级的数量；(2)动态控制LNA级的正反馈和偏置，以便根据信号强度和干扰来权衡功率、信号处理和噪声系数；(3)将电荷泵集成到单个漏极电源中。优化rf关键阶段的电压，同时允许CMOS芯片的非关键部分在低电压下工作。成功实施将提高无线传感器的工作范围和使用寿命，在不利干扰条件下实现更可靠的通信，并最终使信息技术在工业和科学领域得到更广泛的应用。

There is a rapidly growing trend toward embedding wireless capability into a wide variety of information technology products; recently in the form of single chip transceivers, and in the future perhaps integrated on-chip with the main product function. These devices must have low power consumption to satisfy battery conservation and thermal considerations. Good receiver sensitivity and signal handling are also essential in a crowded radio frequency (RF) spectrum; however, this requirement conflicts with low power circuit design. We propose to develop low power CMOS circuits that improve the trade-off between power consumption and RF performance. Current CMOS low noise amplifiers (LNA) have noise figures as low as 0.8 dB, input intercept points up to +18dBm, and power as low as 1.5 mW; however, these specifications cannot be obtained simultaneously. Likewise, CMOS mixers can meet demanding CDMA communications standards for linearity and noise figure, but only at high power cost.To address these problems we propose a number of strategies for (a) reducing power consumption for a given level of performance, and (b) allowing a dynamic trade-off of power versus RF performance. These trategies include: (1) reuse of amplifier stages at two different frequencies through reflex arrangements, thus reducing the number of high performance, high current stages required in receivers, (2) dynamically controlled positive feedback and bias in LNA stages, to allow power, signal handling, and noise figure to be traded off based on signal strength and interference, and (3) integration of charge pumps into individual drain supplies, to optimize the voltage for RF-critical stages while allowing the non-critical portions of a CMOS chip to operate at low voltage.Successful implementation will lead to improved range and life for wireless sensors, more reliable communications under adverse interference conditions, and ultimately to wider application of information technology in industry and science.