Compiling for and Designing Next Generation Memory Systems

实现计算机高性能的最紧迫的障碍是CPU的计算速度比计算机将数据传送到CPU的速度快。由于程序通常有规律的重复访问，当前的计算机将最近访问的数据缓存在快速、扁平的存储器层次结构中，以提高性能。技术趋势使数据传输问题变得更加严重，并将迫使内存设计（如分区缓存级别）发生变化。 我们提出了一个丰富的软件/硬件接口来管理下一代缓存。 我们提出了新的编译器算法来翻译程序，使其在这种新的硬件上执行得更好，并提出了新的硬件设计，使编译器能够通知硬件当前和未来的数据访问时间。 这些新技术将远远超出当前最低限度的加载和存储架构/编译器接口，以提高性能。其结果将使计算机系统的最终用户能够更快、更容易地解决他们的问题。 本文的研究成果将对高速缓存的软硬件体系结构的设计和实现产生广泛的影响. 它将为编译器、工具和模拟国家研究基础设施增加新的和增强的工具。这项工作也将培养高级研究的研究生。

The most pressing obstacle to achieving high computer performance isthat CPUs compute faster than the computer can move data to the CPU. Because programs usually have regular and repetitive accesses, currentcomputers cache recently accessed data in a hierarchy of fast, flatinclusive memories to improve performance. Technology trends aremaking the data delivery problem much worse and will force changes toto memory design such as partitioned cache levels. We propose a richsoftware/hardware interface to manage next generation caches. Wepropose new compiler algorithms to translate programs to performbetter on this new hardware, and new hardware designs that enable thecompiler to inform the hardware of current and future data accesspatterns. These new techniques will go well beyond the currentminimalist load and store architecture/compiler interface to achievehigh performance. The result will enable end users of computer systemsto solve their problems more quickly and easily. The research willhave broad impact on the design and implementation of software andhardware cache architectures. It will add new and enhanced tools tothe compiler, tool, and simulation national research infrastructure.This work will also train graduate students in advanced research.