SGER: Evaluating Reliability of Defect Tolerant Architectures for Nanotechnology using Probabilistic Model Checking

随着摩尔定律所预测的硅技术的进步，我们已经进入了器件特征尺寸的深亚微米时代。目前，90纳米(90纳米)是现实，很快我们就会达到几十微米。届时，这项技术将发生翻天覆地的变化，出现单电子晶体管等纳米技术时代的文物。因此，在如此微不足道的量子技术水平下，设备行为的不确定性将是工程师必须处理的常见问题。目前，在设计计算机体系结构组件时，工程师们安全地假设晶体管和逻辑门的行为将如理论所预测的那样。然而，随着纳米技术中不确定性的猖獗，人们只能依靠晶体管正确运行或逻辑门正确运行的概率来衡量。因此，为了实现逻辑功能并以高度的可靠性依赖它，工程师将不得不在设计中建立冗余，以便如果一些门发生故障，即使在那时，功能块也将以非常高的可靠性提供正确的功能。然而，如何为特定的逻辑功能建立冗余，多少冗余是足够的，以及在什么冗余级别上，可靠性实际上降低了，这是在将这种冗余构建到系统中之前由工程工具来回答的问题。冯·诺伊曼研究了逻辑门的类似问题，因为在他那个时代，逻辑门是用相当不可靠的阀门建造的。信息理论家也用逻辑函数的噪音容忍度来研究类似的问题。然而，不存在用于此类评估的工具，也不存在精确的工程方法。该项目旨在引入新的概率模型检查技术，并创建一套方法和工具集，用于评估不同备用冗余体系结构的可靠性，并在设计建立之前计算可靠性测量，以指导工程师正确的方向。这项工作将帮助计算机工程师在不可靠的纳米衬底上建立可靠的功能，因为材料科学家可以校准纳米材料的故障概率。因此，这项工作将对未来的计算机工程和逻辑设计产生重大影响。此外，它还将有助于培养未来的工程师面对纳米时代，并建立可靠的计算基础设施。

With the advances in silicon technology as predicted by Moore's law, we are already in deep sub-micron era of device feature size. Currently 90 nanometer (90 nm) is a reality, and very soon we will be in the tens of microns. The technology will then change drastically, with single electron transistors and such artifacts of nano-technology era. As a result, uncertainties about the device behaviors will be a common problem that engineers will have to deal with, in such miniscule quantum level of technology. Currently, while designing computer architecture components, engineers safely assume that the transistors and logic gates will behave as predicted by the theory. However, with uncertainties being rampant in nano-technology, one can only rely on the measures of the probability that a transistor will behave correctly, or a logic gate will function correctly. As a result, in order to implement a logic function and to depend on it with high degree of reliability, engineers will have to build redundancy in the design, such that if some of the gates fail, even then, the functional block will provide the correct functionality with very high degree of reliability. However, how to build redundancy for particular logic functions, and how much redundancy is enough, and at what level of redundancy, the reliability actually decreases, are questions to be answered by an engineering tool, before such redundancy is built into the system. Von Neumann looked at similar problems for logic gates since during his time, logic gates were built with valves which were quite unreliable. Information theorists also look at similar problems in terms of noise tolerance by logic functions. However, no tool exists for such evaluations, nor does a precise engineering methodology exist. This project aims at bringing in the novel technology of probabilistic model checking and create a methodology and tool set for evaluation of reliability for different alternate redundant architectures and compute reliability measures before the design is built to steer the engineers in the right directions. This work will help prepare computer engineers in building reliable functionalities on unreliable nano-substrates, given that material scientists can calibrate nano-materials for probability of failures. This work therefore will have great impact in the future computer engineering and logic design. Also it will help educate future engineers to face the nano era and build reliable computing infrastructures.