EAGER: A Novel Approach to Application Specific Instruction Processor Synthesis from Polychronous Specifications

复杂的嵌入式系统包含大量的传感器、执行器和大量的微控制器或嵌入式处理器，这需要复杂的多线程编程和有条件的同步。手动实现这种软件的任务是容易出错的，导致严重的错误，因此需要昂贵的验证。 由于实施后验证的固有困难，本项目采取了通过构造来合成正确的系统的方法。这个项目使用了一个polyclonal数据流规范语言，它自然地适合于多线程软件合成。在这个项目中开发的理论和工具将使软件/硬件合成从同一个规范，这可能有一个显着的影响，为广泛的安全关键的嵌入式systems.This项目提供了一个新的语义polyclonal规范语言的形式的条件偏序，并利用这种语义开发算法的应用程序特定的处理器合成。为了合成处理器，研究人员确定所需的指令集，并优化其实现，而实现功能的微代码程序的合成是由调度合成得出的。

Complex embedded systems contain a multitude of sensors, actuators, and a number of micro-controllers or embedded processors, which require complex multi-threaded programming with synchronizations that are conditional. The task of implementing such software manually is error-prone leading to crucial errors, and hence require expensive validation. Due to inherent difficulties of post-implementation verification, this project takes the approach of synthesizing systems that are correct by construction. This project uses a polychronous data-flow specification language which lends itself naturally to multithreaded software synthesis. The theory and tools developed in this project will enable software/hardware synthesis from the same specification which could have a significant impact for a wide array of safety-critical embedded systems.This project provides a new semantics to polychronous specification languages in the form of conditional partial orders, and utilizes this semantics to develop algorithms for application specific processor synthesis. To synthesize the processor, the investigators identify the instruction sets required, and optimize their implementations, while the synthesis of the micro-code programs to implement the functionalities are derived by schedule synthesis.