EAGER: A Novel Approach to Application Specific Instruction Processor Synthesis from Polychronous Specifications

复杂的嵌入式系统包含大量的传感器、执行器和许多微控制器或嵌入式处理器，这需要复杂的多线程编程和有条件的同步。手动实现这类软件的任务容易出错，从而导致关键错误，因此需要昂贵的验证。由于实施后验证的固有困难，本项目采取了通过建设综合正确的系统的方法。该项目使用一种多时数据流规范语言，该语言自然适合于多线程软件合成。该项目所开发的理论和工具将使同一规范的软硬件综合成为可能，这将对广泛的安全关键嵌入式系统产生重大影响。该项目以条件偏序的形式为多时规范语言提供了一种新的语义，并利用该语义来开发专用处理器综合的算法。为了综合处理器，研究人员识别所需的指令集，并优化其实现，而实现功能的微代码程序的综合是通过调度综合得出的。

Complex embedded systems contain a multitude of sensors, actuators, and a number of micro-controllers or embedded processors, which require complex multi-threaded programming with synchronizations that are conditional. The task of implementing such software manually is error-prone leading to crucial errors, and hence require expensive validation. Due to inherent difficulties of post-implementation verification, this project takes the approach of synthesizing systems that are correct by construction. This project uses a polychronous data-flow specification language which lends itself naturally to multithreaded software synthesis. The theory and tools developed in this project will enable software/hardware synthesis from the same specification which could have a significant impact for a wide array of safety-critical embedded systems.This project provides a new semantics to polychronous specification languages in the form of conditional partial orders, and utilizes this semantics to develop algorithms for application specific processor synthesis. To synthesize the processor, the investigators identify the instruction sets required, and optimize their implementations, while the synthesis of the micro-code programs to implement the functionalities are derived by schedule synthesis.