EAGER: A Novel Approach to Application Specific Instruction Processor Synthesis from Polychronous Specifications

复杂的嵌入式系统包含大量的传感器、执行器和许多微控制器或嵌入式处理器，这需要复杂的多线程编程和有条件的同步。手动实现这种软件的任务很容易出错，从而导致重大错误，因此需要昂贵的验证。由于实施后验证的固有困难，本项目采取的方法是通过构建来综合正确的系统。该项目使用了一种多时间数据流规范语言，这种语言很自然地适合多线程软件合成。在这个项目中开发的理论和工具将使软件/硬件能够从相同的规范中合成，这可能对广泛的安全关键型嵌入式系统产生重大影响。本项目以条件偏序的形式为多时间规范语言提供了一种新的语义，并利用这种语义开发特定于应用程序的处理器合成算法。为了合成处理器，研究人员确定了所需的指令集，并优化了它们的实现，而实现功能的微码程序的合成则是通过调度合成得到的。

Complex embedded systems contain a multitude of sensors, actuators, and a number of micro-controllers or embedded processors, which require complex multi-threaded programming with synchronizations that are conditional. The task of implementing such software manually is error-prone leading to crucial errors, and hence require expensive validation. Due to inherent difficulties of post-implementation verification, this project takes the approach of synthesizing systems that are correct by construction. This project uses a polychronous data-flow specification language which lends itself naturally to multithreaded software synthesis. The theory and tools developed in this project will enable software/hardware synthesis from the same specification which could have a significant impact for a wide array of safety-critical embedded systems.This project provides a new semantics to polychronous specification languages in the form of conditional partial orders, and utilizes this semantics to develop algorithms for application specific processor synthesis. To synthesize the processor, the investigators identify the instruction sets required, and optimize their implementations, while the synthesis of the micro-code programs to implement the functionalities are derived by schedule synthesis.