Selective Way Activation of Set-Associativity Caches: Low-Power Design and Test

今天的社会高度依赖便携式数字设备，如手机、PDA、笔记本电脑、MP3播放器、数码相机/摄像机等。使用这些设备时，电池寿命是主要关注的问题之一。缓存已经占了整个CPU芯片动态和泄漏能量的很大一部分(30%-60%)，未来的计算机系统将使用更大的缓存，这将消耗更多的功率。因此，降低缓存系统的功耗是一个重要的研究课题。通常使用集关联缓存，因为它们比直接映射缓存导致的未命中更少。另一方面，它们通常具有较慢的命中时间和较高的功耗，因为多个标签和数据库是并行探测的。本项目的目标是检查地址亲和性和部分比较信息，这些信息可以用来降低操作缓存组关联性，从而节省缓存访问能量，有时甚至可以节省访问延迟。将研究两种新的缓存体系结构，以显著降低组关联缓存的动态功耗。其他研究主题包括新的故障模型、测试方法以及使用休眠高速缓存技术实现低泄漏功耗电路的高速缓存的容错设计。

Today's society highly depends on portable digital devices such as cell phones, PDAs, laptop computers, MP3 players, digital cameras/camcorders, etc. Battery life is one of the major concerns when using these devices. Caches have accounted for a significant fraction (30-60%) of the overall CPU chip dynamic and leakage energy, and tomorrow's computer systems will use even larger caches which will consume more power. Thus lowering the power-consumption of a cache system is an important research topic. Set-associative caches are commonly used because they incur fewer misses than direct-mapped caches. One the other hand, they typically have slower hit times and higher power consumption, because multiple tag and data banks are probed in parallel. The goal of this project is to examine address affinity and partial comparison information which can be used to reduce operational cache set-associativity, thus save cache access energy and some times even access latency. Two new cache architectures will be studied to significantly reduce the dynamic power consumptions for set-associative caches. Other research topics include new fault models, test methods, and fault-tolerant designs for cache memories that implement low-leakage power dissipation circuits using the drowsy cache technique.