Self-Adjusting Architectures/Circuits for Improved Performance and Reduced Design Complexity

纳米集成电路的最新趋势不会被当代的体系结构创新所缓解，并将在未来的微处理器设计中引入重大瓶颈。首先，高性能电路的模型越来越复杂，因此很难确定可以帮助架构师优化设计的关键特性。其次，工艺参数以及电源和温度等环境变量的可变性越来越大。随着越来越多的制造芯片无法达到性能目标，这些不断增加的差异直接反映在微处理器产量统计数据中。此外，通过不直接考虑电路级原因的架构修改来恢复这些损失将是困难的，如果不是不可能的话。在没有干预的情况下，未来处理器的设计周期将被与模型复杂性和参数变化相关的详尽验证所主导。该项目提供了一种范式转换，在设计周期中重点分析了可能的故障，并增加了自我监控、自我调整机制，既可以提高成品率，增加性能，又可以减少验证要求。这种方法的核心是能够容忍变化的灵活架构的设计。具体地说，该项目涉及：(1)基于物理特性的变化感知体系结构模型，其对于处理器中的关键段和可能的故障的初始估计以及权衡研究是必不可少的；(2)创新的自调整体系结构，其考虑了电路的物理方面，并且可以基于现场读数进行重新配置；(3)用于在芯片上放置传感和监控元件的算法，以及自适应结构的部署和所需自适应类型的确定；以及(4)电路综合算法，其确定如何调整处理器以提高成品率和性能。该项目直接解决了微处理器行业的一个关键问题：工艺变化，因此将具有显著的商业和社会效益。学术上的好处包括设计自动化、电路和架构研究人员与教育工作者之间的密切互动。这将为学习开辟新的途径，并带来一系列新的有趣挑战。

Recent trends of nanoscale integrated circuits will not be mitigated by contemporary architectural innovations and will introduce significant bottlenecks in the design of future microprocessors. First, the growing complexity of models for high performance circuits make it difficult to identify critical characteristics which could aid architects in optimizing the design. Second, there is an increasing variability both in the process parameters and in environmental variables such as power supply and temperature. These increasing variations are directly reflected in microprocessor yield statistics as more manufactured chips fail to meet performance targets. Furthermore, it will be difficult if not impossible to recover from these losses with architectural modifications, which do not directly consider the circuit level causes. Without intervention, the design cycle of future processors will be dominated by exhaustive verification related to model complexity and parameter variation. This project offers a paradigm shift where the design cycle features focused analysis of possible failures and the addition of self-monitoring, self-adjusting mechanisms that can both improve the yield, increase the performance, and reduce the requirements of verification. At the heart of this approach lies the design of flexible architectures that can tolerate variations. Particularly, this project involves generation of: (1) variation-aware architectural models which are based on physical properties and are essential for an initial estimate of the critical segments in the processor and possible failures, as well as tradeoff studies, (2) innovative self-adjusting architectures which consider physical aspects of circuits and can be reconfigured based on in-field readings, (3) algorithms for placement of sensing and monitoring elements on the chip as well as the deployment of the adaptive structures and determination of the adaptation type needed, and (4) circuit synthesis algorithms, which determine how to adjust processors for improved yield and performance. This project directly attacks a critical problem in the microprocessor industry: process variation, and hence would have significant commercial and social benefits. Academic benefits include the close interaction between the design automation, circuits, and architecture researchers and educators. This will open new avenues for learning and present a new set of interesting challenges.