CAREER: Practical Transactional Memory for Highly Parallel Systems

随着单处理器系统面临功耗和设计复杂性等基本限制，单芯片多处理器为服务器、嵌入式和桌面应用程序提供了一条实现可扩展性能的现实途径。然而，限制多处理器体系结构潜力的关键因素是开发并行程序的难度。现有的具有基于锁的同步的多线程模型在功能正确性和性能之间引入了复杂的权衡，这是大多数程序员无法掌握的。基于众所周知的数据库原子事务概念，事务内存为多处理器中的并发管理提供了另一种模型。该项目将开发新的多处理器架构，以有效地实现事务内存。第一个目标是定义支持直观并行编程模型的事务内存的体系结构语义。第二个目标是开发在单芯片多处理器系统中提供高性能的事务存储器的实用硬件实现。该项目将导致同步和并发管理的硬件和软件接口的重组，并将为易于编程、执行成本效益高和速度快的多处理器铺平道路。该项目还将为学生提供开发和有效编程用于服务器、嵌入式和桌面应用的下一代单芯片多处理器所需的知识和技能。

With uniprocessor systems running into fundamental limitations such as power consumption and design complexity, single-chip multiprocessors provide a realistic path toward scalable performance for server, embedded, and desktop applications. Nevertheless, the key factor limiting the potential of multiprocessor architectures is the difficulty of developing parallel programs. Existing multithreading models with lock-based synchronization introduce complex tradeoffs between functional correctness and performance that most programmers cannot master. Transactional memory provides an alternative model for concurrency management in multiprocessors based on the well-known database concept of atomic transactions. This project will develop new multiprocessor architectures to efficiently implement transactional memory. The first goal is to define the architectural semantics of transactional memory that support intuitive parallel programming models. The second goal is to develop practical hardware implementations of transactional memory that provide high performance in single-chip multiprocessor systems. The project will result in a restructuring of the hardware and software interfaces for synchronization and concurrency management and will pave the way towards multiprocessors that are easy to program, cost-effective to implement, and fast. The project will also provide students with the knowledge and skills necessary to develop and efficiently program the next generation of single-chip multiprocessors for server, embedded, and desktop applications.