SHF: Medium: Energy Efficient Memory Systems

该项目的目标是开发节能系统。提高能源效率是信息技术面临的一个决定性挑战，也是提高从智能手机到仓库规模数据中心的所有计算系统能力的先决条件。这一领域的大多数研究都集中在使用专用内核或近阈值电压电路的节能计算上。为了实现端到端的能源效率，还必须优化为内核提供数据和指令的片上和片外存储器系统。存储系统包括大的，泄漏的结构和通信操作，引入的能量开销比计算操作的开销高出几个数量级。本项目提出了一种全面的方法来提高能量效率的存储系统，重新考虑存储系统架构，动态运行时管理和电路设计。在架构层面，它将优化新兴的，以数据为中心的应用程序与有限的时间局部性，将计算靠近内存结构，使能源密集型通信最小化。 它还将探索对内存系统中的专门化的架构支持，例如专门的预取，数据转换和数据分发引擎。在运行时管理层面，它将研究可扩展的调度算法，通过最大限度地提高时间和空间的局部性以及使用片上和内存侧加速器来最大限度地减少内存系统中的能源使用。在电路设计层面，它将积极优化内存芯片和内存堆栈的内部结构的能量消耗的主导访问模式后，有效的运行时管理。最后，这个项目将创建工具，共同探索的架构管理调度空间，以确定帕累托最优的内存系统的不同水平的性能。

The goal of this project is to develop energy efficient systems. Improving energy efficiency is a defining challenge for information technology and the prerequisite to increasing the capabilities of all computing systems, from smartphones to warehouse-scale data-centers. Most research in this area has focused on energy efficient computing, using specialized cores or near-threshold voltage circuits. To achieve end-to-end energy efficiency, the on-chip and off-chip memory system that feeds cores with data and instructions must also be optimized. The memory system includes large, leaking structures and communication operations that introduce energy overheads orders of magnitude higher than the overheads of compute operations.This project proposes a holistic approach towards energy efficient memory systems that rethinks memory system architecture, dynamic runtime management, and circuit design. At the architecture level, it will optimize for emerging, data-centric applications with limited temporal locality by placing computing close to the memory structures so that energy intensive communication is minimized. It will also explore architectural support for specialization in the memory system, such as engines for specialized prefetch, data transformations, and data distribution. At the runtime management level, it will investigate scalable scheduling algorithms that minimize energy usage in the memory system by maximizing temporal and spatial locality and the use of on-chip and memory-side accelerators. At the circuit design level, it will aggressively optimize the energy consumption of the internal structures of memory chips and memory stacks for the dominant access patterns after efficient runtime management. Finally, this project will create tools for joint exploration of the architecture-management-scheduling space in order to identify Pareto optimal memory systems for different levels of performance.