NGS: A Design Environment for Single Chip Heterogeneous Multiprocessors

在未来五年内，将有可能在单个芯片上提供足够的晶体管，用于100个ARM等效处理器。在这一点上，个人，可编程处理器将像寄存器是早期的超大规模集成电路设计-构建块在一个更大的组织框架。 研究人员将这类设备称为可编程异构多处理器（PHM），强调不仅芯片上的单个处理器是可编程的，而且芯片上的处理器集合以及整个芯片都必须被视为可编程的。可能出现在这样的设备上的应用包括当前的蜂窝电话、当前的个人数字助理（PDA）应用、全球定位系统（GPS）感测、蓝牙、运动感测、自组织联网、3-D图像处理、压缩/解压缩、安全、多媒体和广泛的人机交互（HCI）软件。无处不在和普及的计算将产生具有更复杂功能的更新场景。但这些可能性受到在个人空间和功率受限的计算设备中设计和技术实现这些场景的能力的限制。 单芯片计算类，将离开桌面，以满足未来的计算需求提出了明显不同的编程和设计挑战，从板和网络级异构多处理器，因为一个单一的芯片是一个有限的资源，硬件设计将是半定制的，系统资源的协调将是必需的。所有这些都说明了消费电子设备由于其物理限制而需要的优化水平。该项目将研究新的设计策略，这些策略利用下一级设计，因为可以通过减少建模细节来评估系统性能。该方法将定义拟议功能和多处理器架构的新视图，从而实现整个系统性能的模拟和优化。新颖的，建议的策略包括开发的设计方案，这是回答目前单独的视图的测试台，行使计算机系统和基准，用于评估可编程设计，并启用新的系统级策略，以节省电力，使用大量的简单的处理器，在较低的时钟速率或复杂的多处理器级调度策略执行。虽然雄心勃勃，该项目的愿景是启用，因为以前的工作，在开发一种新的模拟器，捕捉性能的并发软件执行并发硬件使用分层模型的相互作用。

Within the next five years, it will be possible to provide enough transistors on a single chip for on the order of a hundred ARM-equivalent processors. At that point, individual, programmable processors will be like registers were to early VLSI design - building blocks within a larger organizing framework. The investigators refer to this class of devices as Programmable Heterogeneous Multiprocessors (PHMs), emphasizing that not only will individual processors on the chip be programmable, but collections of processors on the chip as well as the chip as a whole must be considered programmable. Applications that might appear on such devices include that of current cell phones, current personal digital assistant (PDA) applications, global positioning system (GPS) sensing, Bluetooth, motion sensing, ad hoc networking, 3-D image processing,compression/decompression, security, multimedia and a broad set of human computer interaction(HCI) software. Ubiquitous and pervasive computing will produce newer scenarios with even more complex functionality. But these possibilities are limited by the ability to design and technically realize these scenarios in the individual space and power-constrained computing devices. The class of single-chip computing that will leave the desktop in meeting the needs of future computing poses distinctly different programming and design challenges from board and network-level heterogeneous multiprocessors because a single chip is a finite resource, the hardware design will be semi-custom, and coordination of system resources will be required. All of these speak to levels of optimization that will be required for consumer electronic devices because of their physical limitations.The project will investigate new design strategies that leverage the next level of design that is enabled as system performance can be evaluated with reduced modeling detail. The approach will define novel views of the proposed functionality and multiprocessor architecture, enabling simulation and optimization of the whole system's performance. Novel, proposed strategies include the development of design scenarios, which are the answer to the currently separate views of testbenches that exercise computer systems and benchmarks that are used to evaluate programmable designs, and the enabling of novel system-level strategies to save power by using a larger number of simpler processors that execute at lower clock rates or with sophisticated multiprocessor-level scheduling strategies. While ambitious, the project's vision isenabled because of prior work in developing a novel simulator that capture the performance interactions of concurrent software executing on concurrent hardware using a layered model.