SBIR Phase I: VLSI Clocking Using BDS Technology

这个小型企业创新研究（SBIR）第一阶段研究项目将验证双向信令（BDS）概念在超大规模集成电路（VLSI）时钟分配应用。BDS概念是最近引入的一个想法，它为VLSI时钟提供了一种颠覆性的新技术，在VLSI设计方法学中具有重要意义。与最近的其他研究思路类似，BDS用电磁波传播取代了传统有源树中固有的耗散和噪声信号传输，实现了功耗、抖动和传输时间的大幅降低。BDS是一个宽带、开环（驱动）系统，自然支持快速时钟启动/停止操作和非常宽的时钟频率范围。此外，与任何其他VLSI时钟技术不同，BDS将信号传输功能从局部区域负载效应中分离出来，几乎完全自由地进行时钟分配路由。如果BDS的理论承诺变成现实，并且VLSI芯片制造商采用这种技术，那么显著的好处将包括更快的IC开发周期，更低的IC成本，更高的产量和更好的性能。

This Small Business Innovation Research (SBIR) Phase I research project will validate the Bi-Directional Signaling (BDS) concept in Very Large Scale Integrated Circuits (VLSI) clock distribution applications. The BDS concept was introduced recently as an idea enabling a disruptive new technology for VLSI clocking with significant implications in the VLSI design methodology. Similar to other recent research ideas, BDS replaces the dissipative and noisy signal transport inherent in conventional active trees with electromagnetic wave propagation, accomplishing major reductions in power dissipation, jitter, and travel time. BDS is a wide-band, openloop (driven) system naturally supporting fast clock start/stop operations and a very wide range of clock frequencies. In addition, unlike any other VLSI clocking techniques, BDS decouples the signal transport function from the local-area loading effects for almost complete freedom in clock distribution routing. If the theoretical promises of BDS turn into reality and the VLSI chip manufactures adopt this technology, the significant benefits will include faster IC development cycles, lower IC cost, higher yields, and better performance.