CSR--EHS: Collaborative Research: Hybrid Timing Analysis via Multi-Mode Execution

当前安全关键嵌入式系统的软件设计要求严格遵守编码标准，以确保安全性和可靠性。实时嵌入式系统的一个关键附加要求是软件组件的可预测时序行为，这要求确定嵌入式软件的最坏情况执行时间（WCET）的界限。虽然静态时序分析产生的WCET可验证的界限，它不能跟上架构创新和硬件性能的变化，由于芯片制造规模。这项工作提供了一个全新的方法来界定WCET有三个主要贡献：（1）而不是模拟执行，在硬件中的实际执行是促进评估任务的WCET。这种方法不仅不需要繁琐的硬件建模，而且无论体系结构复杂性或硬件变化如何，都可以确认正确的行为。 (2)通过FPGA综合评估了该方法及其复杂度。 这评估了设计的可行性，并验证了原型实现。(3)先进的建筑功能的影响进行了研究，在共同设计的空间探索，旨在提供可预测性和紧密的WCET界限。 在这个项目中进行的研究通过提供执行时间的高置信度界限，通过安全关键嵌入式实时系统的硬件和软件设计的新技术推进现有的科学和技术;增强硬件架构，支持评估执行时间;通过协同设计定制硬件功能，以提高可预测性。 这些能力直接有益于软件控制的安全性和可靠性，例如，飞机和汽车的组件，从而有助于嵌入式系统的高置信度设计。

Current software design for safety-critical embedded systems requires stringent compliance with coding standards to ensure safety and reliability. A key additional requirement for real-time embedded systems is predictable timing behavior of software components, which requires that bounds on the worst-case execution time (WCET) of embedded software be determined. While static timing analysis yields verifiable bounds on the WCET, it cannot keep pace with architectural innovations and hardware performance variation due to chip fabrication scaling. This work contributes a fundamentally new approach to bounding the WCET with three major contributions: (1) Instead of simulating execution, actual execution in hardware is promoted to assess the WCET of a task. This approach not only renders tedious hardware modeling unnecessary but also confirms correct behavior regardless of architectural complexity or hardware variation. (2) The approach and its complexity are evaluated by FPGA synthesis. This assesses the feasibility of the design and validates a prototype implementation. (3) The impact of advanced architectural features is studied in a co-design space exploration, aimed to provide predictability and tight WCET bounds. The research conducted in this project advances existing science and technology through novel techniques in hardware and software design for safety-critical embedded real-time systems by providing high-confidence bounds on execution times; enhancing hardware architectures with support to assess execution times; and customizing hardware features via co-design to improve predictability. These capabilities directly benefit safety and reliability of software controlling, for example, aircraft and components of cars, thereby aiding the high-confidence design of embedded systems.