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Collaborative Research: CSR-EHS: Pret: Precision Timed Architectures

Collaborative Research: CSR-EHS: Pret: Precision Timed Architectures
协作研究:CSR-EHS:Pret:精确定时架构
批准号:
0720882
负责人:
Edward Lee
金额:
$55.0万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2007
资助国家:
美国
项目状态:
已结题
起止时间:
2007-08-01 至 2013-12-31

项目摘要

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中文摘要
翻译
当前在计算中使用的抽象隐藏了软件的时序属性。因此,计算机科学家开发了一些技术,以牺牲时间可预测性为代价,提高了平均情况下的性能和/或设计的便利性。对于与物理进程密切交互的嵌入式软件来说,计时通常是一个基本属性。核心抽象中缺乏时效性会导致脆弱和不可移植的设计。此外,随着嵌入式软件的网络化程度越来越高,目前流行的基于经验测试的实时计算方法变得不足。本项目重新引入时序可预测性作为嵌入式处理器体系结构的一流属性。它从硬件设计的角度解决了这个问题,开发了精密定时(PRET)机器作为现场可编程门阵列的软核。它表明,Pret机器上的软件可以与传统上纯粹的硬件设计集成在一起。这个项目寻求重振计算机科学和计算机体系结构领域的研究,这些领域由于成熟的工业实践而在研究中停滞不前。预计这将为一场长达数十年的革命提供一个起点,这场革命将再次使时序可预测性成为处理器的基本特征。这个项目解决了计算的核心抽象问题。这个项目不是试图用更多的抽象层来纠正这些抽象中缺乏时序的问题,而是旨在展示嵌入式处理器可以提供可预测的时序和高性能。它为新的计算抽象打开了领域,其中包括将计时作为一流属性。
英文摘要
Abstractions currently used in computing hide timing properties of software. As a consequence, computer scientists have developed techniques that deliver improved average-case performance and/or design convenience at the expense of timing predictability. For embedded software, which interacts closely with physical processes, timing is usually an essential property. Lack of timing in the core abstractions results in brittle and non-portable designs. Moreover, as embedded software becomes more networked, the prevailing empirical test-based approach to achieving real-time computing becomes inadequate.This project reintroduces timing predictability as a first-class property of embedded processor architectures. It tackles the problem from the hardware design perspective, developing precision timed (PRET) machines as soft cores on FPGAs. It shows that software on PRET machines can be integrated with what would traditionally have been purely hardware designs. This project seeks to reinvigorate research in an area of computer science and computer architecure that have stagnated in research due to maturing industrial practice. This is expected to provide a starting point for a decades-long revolution that will once again make timing predictability an essential feature of processors. This project addresses the core abstractions of computing. Rather than attempting to correct the lack of timing in these abstractions with more layers of abstraction, this project has the goal of showing that embedded processors can deliver both predictable timing and high performance. It opens up the field to new computing abstractions that include timing as a first-class property.
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