CDI-Type II: Inference at the Nanoscale

该项目的目标是开发一种新的基于推理的信息处理结构，使用全新的纳米设备执行概率计算。这种方法利用了这类设备的模拟、依赖时间的特性以及它们的巨大并行性。通过这样做，这样的计算结构将比使用更传统的数字硬件更有效和可扩展。这种方法是第一批包括时间相关电路元件的方法之一，以建立模拟联想存储器，其近似贝叶斯推理，并进而被组装成捕获数据流中的更高阶结构的复杂网络。最终目标是利用这些电路开发场自适应贝叶斯阵列(FABA)的CMOS/分子混合实现，它有可能成为网络使能发现的关键组件。第一个是基于具有时变特性的复杂纳米和分子尺度器件的模拟电路的设计。第二个关注点是创造一种新的半导体元件家族，它将显著增强在广泛的数据和应用程序中支持网络的发现应用。设计模拟纳米电子电路非常困难，这种电路可以在空间和时间上执行推理，并且由动态元件(如膜电阻和膜电容)组成。当人们考虑到世界各地的实验室正在为纳米和分子规模的电子设备开发广泛的复杂设备时，这一点尤其正确。为此，我们定义了一种结合了多层次抽象和可演化计算的探索方法。然后，两个关键发展是针对此类设备的设计探索方法，以及用于数据捕获和推理的大规模并行体系结构。这项研究将探索一种使用纳米电子学来实现新兴应用的新范例，从“自上而下”的系统需求入手，而不是通过寻找新器件概念的应用(“自下而上”)。随着半导体行业为下一步的发展而苦苦挣扎，这里提出的工作可能会为架构、电路和器件的激进新方法提供洞察。这项研究最终将通过增强人类认知并从社会必须处理的各种不同数字数据的财富中产生新知识来造福社会。

The goal of this project is to develop a new inference-based information processing structure that performs probabilistic computing using radically new nanoscale devices. This approach exploits the analog, time-dependent properties of such devices, and their massive parallelism. By doing so, such a computing structure will be more efficient and scalable than by using more traditional digital hardware. This approach is one of the first to include time-dependent circuit elements to build analog associative memories that approximate Bayesian inference, and which are, in turn, assembled into complex networks that capture higher order structure in streams of data. The ultimate goal is to use these circuits to develop hybrid CMOS / molecular scale implementations of a Field Adaptable Bayesian Array (FABA), which has the potential to be a key component for Cyber-Enabled discovery.Cyber-Enabled discovery is addressed in this research in two ways. The first concerns the design of analog circuits based on complex nano and molecular scale devices with time-varying properties. And the second concerns the creation of a new family of semiconductor components that will significantly enhance Cyber-Enabled discovery applications across a wide range of data and applications.Designing analog nano-electronic circuits that perform inference through space and time and which consist of dynamic components (such as mem-resistance and mem-capacitance) is extraordinarily difficult. This is particularly true when one considers the wide range of complex devices that are being developed in laboratories around the world for nano and molecular scale electronics. For this effort we have defined an Exploration Methodology that combines multiple levels of abstraction and evolvable computation.Two key developments then are a design exploration methodology for such devices, and a massively parallel architecture for data capture and inference. This research will explore a new paradigm for using nanoscale electronics for emerging applications by starting with the "top-down" system requirements rather than by finding applications for new device concepts ("bottom-up").As the semiconductor industry struggles with where to go next, the work proposed here may provide insight into radical new approaches to architecture, circuits and devices. This research will ultimately benefit society by enhancing human cognition and generating new knowledge from the wealth of heterogeneous digital data society has to deal with.