Design of Reliable High-Speed Links with Unreliable Circuits

本研究的目标是为高速数字链路创建一种新的抗故障架构，以实现下一代高性能通信和计算系统。该抗故障架构基于最大后验概率（MAP）检测，不仅克服了具有挑战性的信道损伤，而且还克服了接口和定时电路中发生的确定性损伤。MAP检测提供的系统级保护为设计高能效模数转换器（ADC）和基于海量数字门的时序生成提供了新的机会，这些数字门利用了不可靠的深度扩展器件中的变化和错误。MAP检测器本身使用迭代的软消息传递算法来增强，以释放其全部吞吐量潜力，同时提供对底层电路故障的容忍度。本研究开发的新链路技术将提高云计算所需的大型数据中心的计算能力和能源效率。这些技术还通过提供更高效的串行链路（如下一代通用串行总线（USB））来影响个人和移动的计算。该项目的跨学科性质鼓励混合信号电路，数字电路和信号处理研究的紧密结合，并通过研究和行业实习为学生提供优秀的培训。

The objective of this research is to create a new failure-resistant architecture for high-speed digital links to enable the next generation of high-performance communication and computing systems. The failure-resistant architecture is based on maximum a posteriori (MAP) detection and overcomes not only challenging channel impairments, but also deterministic impairments incurred in the interface and timing circuitry. The system-level protection given by MAP detection offers new opportunities in the design of power-efficient analog-to-digital converters (ADCs) and timing generation based on seas of digital gates that exploit the variations and errors in unreliable, deeply scaled devices. The MAP detector itself is enhanced using an iterative, soft message-passing algorithm to unleash its full throughput potential while providing tolerance against underlying circuit failures. The new link techniques developed in this research will improve both the computing capability and the energy efficiency of large data centers needed for cloud computing. The techniques also impact personal and mobile computing by delivering more efficient serial links such as the next-generation universal serial bus (USB). The interdisciplinary nature of this project encourages a tight integration of mixed-signal circuits, digital circuits and signal processing research and provides excellent training to students through research and industry internships.