Collaborative Research: From High-level Synthesis to Layout: a Cross-layer Methodology for Large-scale Reliable IC Design
Collaborative Research: From High-level Synthesis to Layout: a Cross-layer Methodology for Large-scale Reliable IC Design
批准号:
1255846
负责人:
Deming Chen
金额:
$10.5万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2013
资助国家:
美国
项目状态:
已结题
起止时间:
2013-04-01 至 2016-03-31
中文摘要
设计健壮、节能、高设计效率的大规模片上系统(SOCs)是一个极具吸引力的挑战。然而,不同设计层之间缺乏协调,导致设计者在各个设计层做出最坏的假设,导致可靠性/能量/性能联合优化或权衡很差的次优设计。该项目是致力于从高级综合到紧密集成的物理设计的统一抗故障系统的第一个重大努力。它将构建以可靠性为中心、物理感知的高级综合和高级指导的物理设计,以弥合这两个遥远的层之间的差距。还将开发一种新的跨层工程变更单(ECO)框架,以将高层ECO与稳定的物理层ECO相结合。将研究新的工具和方法,并向系统和实体设计界提供新的工具和方法,以提高可靠性,同时提高总体设计生产力和质量。电子产品已经渗透到现代社会,越来越依赖于这些电子系统的可靠运行。然而,设备级扩展正朝着与系统可靠性相反的方向发展。该项目将通过跨层集成来改变现有的SOC设计方法。这项工作的研究将通过出版物和演示文稿、与行业合作者的积极互动以及向课堂和教学实验室注入新的课程材料来广泛传播。主要调查人员将继续努力将妇女和其他代表性不足的少数群体纳入他们的研究方案。他们以前曾接触过K-12的学生,并将继续这样做,以吸引他们中最优秀的人进入工程专业。
英文摘要
Designing robust and energy-efficient large-scale systems-on-chips (SOCs) with high design productivity is a challenge of great interest. However, lack of coordination among different design layers has caused designers to make worst-case assumptions at individual design layers, leading to substantially suboptimal designs with poor reliability/energy/performance co-optimization or tradeoffs. This project is the first major effort dedicated toward a unified failure-resistant system from high-level synthesis to physical design with tight integration. It will build reliability-centric physical-aware high-level synthesis and high-level-guided physical design to bridge the gap between these two distant layers. A novel cross-layer engineering change order (ECO) framework will also be developed to couple high-level ECO with stable physical-level ECO. New tools and methodologies will be studied and provided to the system and physical design community targeting reliability while increasing overall design productivity and quality. Electronics have permeated modern society, which increasingly depends on reliable operations of these electronic systems. However, device-level scaling is heading in the opposite direction from system reliability. This project will transform existing SOC design methodologies through cross-layer integration. Research from this effort will be broadly disseminated through publications and presentations, active interaction with industrial collaborators, as well as infusion of new course material into classrooms and instructional laboratories. The principal investigators will continue their efforts in recruiting women and other underrepresented minorities into their research programs. They have previously reached out to K-12 students and will continue to do so in order to attract the best of them into the engineering profession.
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CAREER: Nano-Centric Design Methodology for Nanoscale FPGAs
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批准号:0746608
-
项目类别:Continuing Grant
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资助金额:$40.0万
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财政年份:2008
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负责人:Deming Chen
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依托单位:
国内基金
海外基金
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