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CAREER: Nano-Centric Design Methodology for Nanoscale FPGAs

CAREER: Nano-Centric Design Methodology for Nanoscale FPGAs
职业:纳米级 FPGA 的纳米中心设计方法
批准号:
0746608
负责人:
Deming Chen
金额:
$40.0万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2008
资助国家:
美国
项目状态:
已结题
起止时间:
2008-08-01 至 2014-07-31

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CCF - 0746608 PI name: Deming ChenTitle: CAREER: Nano-Centric Design Methodology for Nanoscale FPGAsInstitution: University of Illinois at Urbana ChampaignABSTRACT:Conventional top-down manufacturing faces serious challenges due to fundamental physical and economical constraints. Bottom-up approaches, in which integrated functional device structures are assembled from chemically synthesized nanoscale building blocks, such as carbon nanotubes (CNT) and nanowires, have the potential to revolutionize the fabrication of electronic systems for the future. Such nanosystems are by their nature very regular in structure and, therefore, suitable to implementation similar to Field Programmable Gate Arrays (FPGAs). Nanoelectronic circuits always have a certain percentage of defects as well as nanomaterial-specific variations over and above process variations introduced by lithography. Using simplified nanodevice assumptions and traditional scaled design flows will lead to suboptimal and impractical nanoFPGA designs and inaccurate system evaluation results. For nanotechnology to fulfill its promise, we need to understand and incorporate nano-specific design techniques, such as nanosystems modeling, statistical approaches and fault tolerant design, systematically from devices all the way up to systems. Motivated by this observation, this CAREER program proposes a fundamental, systematic and nano-centric design methodology for nanoscale FPGAs. The proposal includes the following four integrated design aspects: 1) Patterning: Designs novel and reliable architecture patterns, such as a new CNT-based one-time-configurable FPGA; 2) Modeling: Develops new device/wire/circuit models considering nanomaterial-specific variations, manufacturing limitations, and defects; 3) Synthesizing: Focuses on novel nano-centric synthesis techniques from the behavior level down to the physical design level; and 4) Evaluating: Builds a new parameterized nanoFPGA evaluation/exploration engine NanoEngine. The PI plans to develop a new interdisciplinary course incorporating nanomaterials fabrication, nanoelectronic principles, programmable ICs, and CAD. The PI has worked and will continue to reach out to K-12 students for micro/nano electronics education through short lecture series, Engineering Open House, and IEEE Teacher In-Service programs. He will also work with university organizations, such as Women in Engineering, to increase the participation of under-represented groups, especially female students. This project is especially compelling to undergraduate students, who are attracted to new technologies and may become the future leaders of nanoelectronic industry.
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Collaborative Research: From High-level Synthesis to Layout: a Cross-layer Methodology for Large-scale Reliable IC Design
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