SBIR Phase I: Low cost, scalable and selective electrochemical TSV fill technology for 3D IC interconnects

这个小型企业创新研究第一阶段项目提出了一种制造3D IC互连的新方法。2D缩放的物理和经济限制（摩尔定律）阻止了进一步增加集成密度以改善集成电路（IC）的性能。这些挑战已经刺激了3D硅通孔（TSV）技术（所谓的“More than Moore”）的发展，以提高器件的速度和带宽，以及降低集成微系统的形状因子和功耗。然而，3D TSV技术的实现受限于3D TSV填充的高成本（由于使用昂贵的气相沉积和化学机械工艺）及其对高TSV纵横比和较小通孔尺寸（以增加I/O）的差的可扩展性（由于物理和化学气相沉积膜的低保形性）。本研究的目的是解决这个问题，以实现高纵横比的3D TSV的成本效益和可靠的填充。这一目标将通过使用新型电化学材料和工艺来实现，这些材料和工艺能够实现共形阳极隔离和无电阻挡/种子膜，以及选择性电化学Cu TSV填充。该项目更广泛的影响/商业潜力将是加速半导体制造中低成本和可扩展TSV技术的大规模采用。美国、欧洲、日本、韩国、台湾等国家和地区的许多公司都在开发3D TSV封装。然而，高成本和低可扩展性的3D TSV填充工艺阻碍了3D IC互连的大规模采用。我们专有的低成本、可扩展和选择性（电化学TSV填充技术）将使我们能够将TSV填充技术的成本降低2倍，并将可扩展性提高3倍，以制造低成本、高速、大带宽和更广泛功能的3D器件。因此，该项目的成功完成不仅将加速3D IC晶圆技术应用于下一代智能手机等最先进的高性能数字设备，从而产生重大的社会影响，而且还将通过创造美国半导体就业机会和保持美国在广泛半导体应用领域的技术领先地位而产生积极的经济影响。

This Small Business Innovation Research Phase I project advances a novel method to fabricate 3D IC interconnects. Physical and economical limitations for 2D scaling (Moore's Law) prevents further increase of integration density to improve the performance of integrated circuits (IC). These challenges have stimulated the development of 3D through-silicon via (TSV) technology (so called 'More than Moore') in order to increase the speed and the bandwidth of the devices as well as to decrease the form factor and power consumption of integrated microsystems. However, the implementation of 3D TSV technology is limited by the high cost of 3D TSV fill (due to the use of expensive vapor deposition and chemical-mechanical processes) and its poor scalability (due to low conformality of physical and chemical vapor deposited films) to high TSV aspect ratios and smaller via sizes (to increase I/O). The objective of this investigation is to address this problem in order to enable cost-effective and reliable fill of high aspect ratio 3D TSVs. This goal will be achieved with the use of novel electrochemical materials and processes enabling conformal anodic isolation and electroless barrier/seed films, as well as selective electrochemical Cu TSV filling. The broader impact/commercial potential of this project will be to accelerate the mass-scale adoption of low cost and scalable TSV technology in semiconductor manufacturing. The development of 3D TSV packaging is carried out by various companies in USA, Europe, Japan, Korea, Taiwan, etc. However, the high cost and low scalability 3D TSV filling process prevents mass-adoption of 3D IC interconnects. Our proprietary low-cost, scalable and selective (electrochemical TSV fill technology will allow us to decrease the cost of TSV fill technology by a factor of 2 and to increase the scalability by a factor of 3 to fabricate low cost, high speed, large bandwidth and broader functionality 3D devices. Therefore, the successful completion of this project would not only have a significant societal impact by accelerating 3D IC wafer technology adoption into state-of-art high performance digital devices such as next generation of smart phones, but also have positive economic impact by creating US semiconductor jobs and maintaining US technology leadership over a wide range of semiconductor applications.