SBIR Phase II: Low cost, scalable and selective electrochemical metallization process technology

这个小型企业创新研究（SBIR）第二阶段项目的更广泛的影响/商业潜力将是通过降低成本和提高3D硅通孔（TSV）互连的可扩展性，利用电化学，低成本和选择性金属化技术来加速3D集成电路（IC）的大规模采用。在其鉴定之后，3D TSV选择性金属化技术将能够通过用用于TSV金属填充、凸块和再分布层形成的选择性电化学金属化技术替代昂贵的MEMS互连技术来以较低的成本制造高性能3D微系统。 该项目的成功完成将加速3D IC晶圆技术在下一代智能手机等最先进的高性能数字设备中的应用，从而产生重大的社会影响。该项目还将通过创造美国半导体就业机会并保持美国在广泛的电子应用和消费电子设备领域的技术领先地位，产生积极的经济影响。这个小型企业创新研究（SBIR）第二阶段项目推进了一种新型的三维硅通孔（TSV）选择性金属化技术，以制造低成本和可扩展的3D集成电路（IC）。二维缩放的物理和经济限制（所谓的“摩尔？s定律）阻止了集成电路进一步提高集成密度以改善集成电路性能。这些挑战已经刺激了3D TSV技术（所谓的“超过摩尔”）的发展，以便增加器件的速度和带宽以及降低集成微系统的形状因子和功耗。然而，3D IC的大规模采用受到3D TSV互连的高成本（由于使用昂贵的气相沉积和化学机械光刻工艺）及其对高深宽比和较小通孔尺寸的差的可扩展性（由于物理和化学气相沉积膜的低保形性）的限制。在第一阶段项目期间开发的专有和专利3D TSV选择性金属化技术将在生产工具上进一步优化和合格，以解决3D TSV互连的成本和可扩展性问题。实现低成本和可扩展的3D IC将允许下一代智能手机和其他消费电子设备的异构系统集成。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project will be to accelerate the mass-scale adoption of 3D integrated circuits (IC) by decreasing the cost and increasing the scalability of 3D through-silicon vias (TSV) interconnects with electrochemical, low cost and selective metallization technology. After its qualification, 3D TSV selective metallization technology will enable fabrication of high performance 3D microsystems at lower cost by replacing costly damascene interconnect technology with selective electrochemical metallization technology for TSV metal fill, bump and redistribution layer formation. The successful completion of this project would have a significant societal impact by accelerating 3D IC wafer technology adoption into state-of-art high performance digital devices such as next generation of smart phones. This project will also have positive economic impact by creating US semiconductor jobs and maintaining US technology leadership over a wide range of electronic applications and consumer electronic devices. This Small Business Innovation Research (SBIR) Phase II project advances a novel three-dimensional through-silicon vias (TSV) selective metallization technology to fabricate low cost and scalable 3D integrated circuits (IC). Physical and economical limitations for two-dimensional scaling (so called "Moore?s Law") prevent further increase of integration density to improve the performance of IC. These challenges have stimulated the development of 3D TSV technology (so called "More than Moore") in order to increase the speed and bandwidth of the devices as well as to decrease the form factor and power consumption of integrated microsystems. However, the mass adoption of 3D IC is limited by the high cost of 3D TSV interconnects (due to the use of expensive vapor deposition and chemical-mechanical damascene processes) and its poor scalability (due to low conformality of physical and chemical vapor deposited films) to high aspect ratios and smaller via sizes. Proprietary and patented 3D TSV selective metallization technology developed during Phase I project will be further optimized and qualified on production tools to address cost and scalability issues of 3D TSV interconnects. Enabling low cost and scalable 3D ICs will allow heterogeneous systems integration for next generation smart phones and other consumer electronic devices.