SBIR Phase I: Multi-Core Sleep Convention Logic Processor

该小型企业创新研究（SBIR）第一阶段项目旨在解决使用新的异步设计技术设计超低功耗电路的挑战，以大幅降低动态功耗和泄漏功耗。 该项目的目标是使用Sleep Convention Logic（SCL）在工业多核处理器上演示改进的功耗特性，SCL是一种异步逻辑，可自动使电路进入睡眠状态以降低泄漏功耗。 一个16核处理器将使用SCL实现，并与同步实现进行比较，两者都采用相同的65纳米技术。 这两种实现都将基于行业标准硬件描述语言（HDL）中描述的相同源设计，并将得到的SCL实现与同步实现进行比较，以证明功能等效。 SCL和同步实现都将针对动态和泄漏功耗、面积和时序进行表征。 预计SCL实现将在面积上稍大一些，并且具有稍慢的时序，但是显著降低了动态和泄漏功率。 表征工作将量化这些比较。 该项目的重要性在于，这将是SCL和纳米制造工艺中工业电路同步实现的第一次比较。该项目更广泛的影响/商业潜力将是建立基于行业标准的异步设计方法，并根据经验量化将SCL用于超低功耗电路和功耗敏感应用的好处。 预计SCL特别适合于采用多个相同内核的片上系统（SoC）设计。 今天，SoC上使用的内核数量通常受到总功耗的限制;如果每个内核的功耗可以显著降低，那么可以放置在SoC上的内核数量可以显著增加。 更多的内核可以提高带宽和能效，从而增强功能，尤其是在依赖高级信号处理的应用中，如高速无线通信、遥感、嵌入式视觉和植入式医疗设备。 助听器只是需要以极低的功耗水平进行大量信号处理的应用的一个示例。 如今，有限的电池寿命是阻碍市场接受和高级助听器的个人便利性的主要问题。 该项目的成果将为缓解这些限制提供一条途径，从而在个人通信和医疗市场等领域开辟新的机会。

This Small Business Innovation Research (SBIR) Phase I project addresses the challenge of designing ultra-low power circuits using new asynchronous design techniques to dramatically reduce both dynamic power and leakage power. The objectives of this project are to demonstrate improved power characteristics on an industrial multi-core processor using Sleep Convention Logic (SCL), a type of asynchronous logic that automatically puts circuits to sleep to reduce leakage power. A 16 core processor will be implemented using SCL and compared to a synchronous implementation, both in the same 65nm technology. Both implementations will be based upon the same source design described in an industry standard Hardware Description Language (HDL) and the resulting SCL implementation will be compared against the synchronous implementation to demonstrate functional equivalency. Both the SCL and synchronous implementations will be characterized for dynamic and leakage power consumption, area, and timing. It is anticipated that the SCL implementation will be somewhat larger in area and have somewhat slower timing, but have significantly reduced dynamic and leakage power. The characterization effort will quantify these comparisons. This project is significant in that this will be the first comparison of SCL and synchronous implementations of an industrial circuit in a nanometer fabrication process. The broader impact/commercial potential of this project will be to establish asynchronous design methodologies based upon industry standards and to empirically quantify the benefits of using SCL for ultra-low power circuits and power sensitive applications. It is expected that SCL is especially well suited to system on chip (SoC) designs that employ a multitude of identical cores. Today, the number of cores used on SoCs is typically limited by total power consumption; if the power consumption of each core can be reduced dramatically, then the number of cores that can be placed on an SoC can be dramatically increased. Larger numbers of cores result in increased bandwidth and energy efficiency, thus enabling increased functionality especially in applications relying upon advanced signal processing such as high-speed wireless communications, remote sensing, embedded vision, and implantable medical devices. Hearing aids are but one example of applications requiring large amounts of signal processing at extremely low levels of power consumption. Today, limited battery life is a major issue inhibiting both market acceptance and personal convenience of advanced hearing aids. Results of this project will provide a path to easing such limitations thereby opening up new opportunities in personal communication and medical markets, among many others.