SBIR Phase I: Radiation Hardened Integrated Circuits for CT Scanners with Reduced Radiation Exposure

这个小型企业创新研究（SBIR）第一阶段项目的目标是在晶体管级别开发抗辐射IC设计技术。这将使使用标准CMOS工艺设计和生产抗辐射器件成为可能，与标准晶体管设计相比，其辐射容限提高了一个数量级。该方法采用了IC晶体管设计和布局方法的创新，在保持标准CMOS集成电路性能的同时，大大提高了其辐射容限。使用现有先进的CMOS IC设计和工艺的能力将使电子产品具有更好的性能，并延长高辐射应用中的电子产品寿命。这项技术的早期应用将是用于CT扫描仪的信号处理电子设备，目的是减少患者和医务人员在CT扫描期间所经历的辐射暴露。该项目将使传感器信号处理器的生产成为可能，传感器信号处理器可以根据需要放置在x射线探测器附近，直接放置在x射线光束路径上，并最终与探测器集成。第一阶段项目的目标是提供概念验证方法，以大大提高标准CMOS设计的集成电路的辐射容限，用于ct扫描仪电子设备和其他高辐射应用。该项目的更广泛的影响/商业潜力将是为ct扫描设备制造商提供制造ct扫描仪的能力，通过将探测器电子设备直接放置在x射线探测器排附近，大大减少了暴露。利用这种改进的辐射暴露技术解决CT扫描设备电子产品市场的关键是能够在标准半导体工艺中设计抗辐射ic。这个项目的目标是通过在现有的商业工艺中使用设计技术来提高集成电路的辐射硬度，而不是通过开发昂贵的新工艺。减少医疗和牙科x光、用于国家安全的全身扫描仪以及相关系统的剂量，将降低社会健康风险和癌症发病率。该项目将加强对CMOS集成电路辐射效应的科学和技术理解，并提供提高其辐射容忍度的方法。在可靠性至关重要的广泛应用中，抗辐射电子设备可以更容易地开发出来。

This Small Business Innovation Research (SBIR) Phase I project targets development of a radiation-hard IC design technology at the transistor level. This will enable the design and production of radiation-hard devices using standard CMOS processing, with an order of magnitude improvement in radiation tolerance compared to standard transistor designs. The proposed approach uses innovations in IC transistor design and layout methods which, while maintaining the performance of standard CMOS integrated circuits, greatly increase their radiation tolerance. The ability to use existing advanced CMOS IC designs and processes will enable better performance from the electronics and extend electronics life in high-radiation applications. An early application of this technology will be the signal processing electronics used in CT scanners, with an objective of reducing radiation exposure experienced by patients and medical personnel during CT scans. This project will enable production of sensor signal processors that could be positioned as close to the X-ray detectors as desired, directly in the X-ray beam path, and ultimately integrated with detectors. The objective of this Phase I project is to provide proof-of-concept of methods to greatly improve the radiation tolerance of integrated circuits in designed in standard CMOS, for use in CT-scanner electronics and other high-radiation applications.The broader impact/commercial potential of this project will be to provide CT-scan equipment manufacturers the capability of building CT-scanners offering significantly reduced exposure by enabling the placement of detector electronics in direct proximity to X-ray detector rows. The key to the ability to address the market for CT scan equipment electronics with this improved radiation exposure technique is the ability to design radiation-hard ICs in standard semiconductor processes. This project targets the improvement of IC radiation hardness by the use of design techniques within existing commercial processes, rather than by developing costly new processes. Dose reductions in medical and dental X-rays, body scanners used for national security, and related systems would reduce societal health risks and the incidence of cancer. The project will enhance scientific and technological understanding of radiation effects on CMOS integrated circuits, as well as providing methods to improve their radiation tolerance. Radiation-hard electronics could be more easily developed for a wide range of applications where reliability is essential.