SBIR Phase II: Radiation-Hardened Integrated Circuits Using Standard Process Flows, and Electronic Design Automation Tool Implementation

SBIR 第二阶段：使用标准工艺流程的抗辐射集成电路和电子设计自动化工具实现

• 批准号: 1456408
• 负责人: Emily Donnelly
• 金额: $ 75万
• 依托单位: APOGEE SEMICONDUCTOR, INC.
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-03-01 至 2018-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1456408&HistoricalAwards=false
• 关键词: SBIR; Phase; II; Radiation; Hardened

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project will be to develop and commercialize radiation-tolerant integrated circuit (IC) technology for producing radiation-tolerant/hardened (rad-hard) ICs capable of being manufactured using leading-edge commercial IC processing instead of expensive specialized processes which use older, less efficient lithography nodes. The direct customers for the technology, to be delivered in the form of Electronic Design Automation (EDA) tools and support services, will be semiconductor integrated device manufacturers and semiconductor foundries. In the CT scanner industry, improved radiation-tolerance of the electronics will allow key components to be placed directly in the X-ray path, improving signal quality, and resulting in better images at reduced X-ray dose levels to patients. Reducing X-ray exposure from CT scans is a medical priority, as it has been estimated that 0.4% of current cancer incidents result from high X-ray doses from CT scans. Application of the patent-pending technology in radiation-hard ICs for a wide range of other commercial radiation-environment markets will follow, including commercial satellites, nuclear-power electronics, nondestructive testing, and medical electronics sterilization. This Small Business Innovation Research (SBIR) Phase II project will provide integrated circuit (IC) designers access to leading-edge IC technology and advanced lithography nodes in developing ICs for radiation-tolerant applications, and is based on patent-pending transistor-level design and layout innovations and their implementation in EDA tools. In Phase I, proof-of-concept was established; transistor structures evaluated for X-ray and gamma radiation tolerance improved by a factor of 7 for 1.8V transistors, and by well over a factor of 10 for 5V transistors, with the use of the technology. The research objective of Phase II is to provide ready access to the benefits of the technology to IC designers by incorporating the methodologies for transistor-level design and layout improvements into industry-standard EDA tools. A number of technical challenges will be addressed in Phase II, including optimizing the tools for producing area-efficient and cost-efficient transistor layouts, and assuring seamless integration with existing design flows. A beta version of an EDA tool kit will be developed in Phase II; the anticipated result will be a tool that can be used by initial customers in producing rad-hard ICs used in CT scan electronics and other applications.

这个小型企业创新研究（SBIR）第二阶段项目的更广泛的影响/商业潜力将是开发和商业化耐辐射集成电路（IC）技术，用于生产耐辐射/加固（抗辐射）IC，这些IC能够使用领先的商业IC处理而不是使用旧的，效率较低的光刻节点的昂贵的专业工艺进行制造。该技术将以电子设计自动化（EDA）工具和支持服务的形式提供，其直接客户将是半导体集成器件制造商和半导体代工厂。在CT扫描仪行业，电子设备的辐射耐受性提高将允许关键组件直接放置在X射线路径中，提高信号质量，并在降低患者X射线剂量水平的情况下获得更好的图像。减少CT扫描的X射线照射是医疗优先事项，因为据估计，目前0.4%的癌症事件是由CT扫描的高X射线剂量造成的。 这项正在申请专利的技术将应用于广泛的其他商业辐射环境市场的抗辐射IC，包括商业卫星，核电电子，无损检测和医疗电子灭菌。该小型企业创新研究（SBIR）第二阶段项目将为集成电路（IC）设计人员提供先进的IC技术和先进的光刻节点，以开发用于耐辐射应用的IC，并基于正在申请专利的晶体管级设计和布局创新及其在EDA工具中的实现。 在第一阶段，建立了概念验证;通过使用该技术，对晶体管结构进行X射线和伽马辐射耐受性评估，1.8V晶体管的耐受性提高了7倍，5V晶体管的耐受性提高了10倍以上。 第二阶段的研究目标是通过将晶体管级设计和布局改进的方法纳入行业标准的EDA工具，为IC设计人员提供快速访问该技术的好处。 第二阶段将解决一系列技术挑战，包括优化用于生产面积效率和成本效益晶体管布局的工具，并确保与现有设计流程的无缝集成。 EDA工具包的测试版将在第二阶段开发;预期的结果将是一个工具，可供初始客户用于生产CT扫描电子和其他应用中使用的抗辐射IC。