SBIR Phase I: Low-density parity-check error correction for enhanced reliability of flash memories

这个小企业创新研究（SBIR）第一阶段项目的更广泛/商业影响是技术和经济的。开发的纠错解决方案将使基于闪存的设备具有更高的容量、更高的可靠性和更快的速度，同时降低成本。这将对移动的计算能力和企业存储产生重大影响，提高数据中心、服务器和包含闪存的关键任务存储的效率和可靠性。改进的企业存储可提高IT业务、电子商务和金融贸易的效率和增长。这些解决方案还将降低功耗和散热，从而实现更环保的系统，这也是经济增长的关键驱动力。从2000年到2012年，美国的GDP增长了23.12%，而所有来源的能源消耗仅增长了3.88%，这一趋势将得到加强。纠错解决方案的好处也适用于硬盘驱动器和通信行业，涉及数千亿美元的收入和两位数的增长率。这个小企业创新研究第一阶段项目是关于开发新的低密度奇偶校验（LDPC）为基础的错误校正闪存为基础的固态硬盘（SSD）。虽然SSD由于其高速度、低功耗和低散热而迅速获得突出地位，特别是在企业存储中，但它们面临着一个主要的扩展问题，因为闪存单元尺寸必须缩小以降低其高成本，导致可靠性不可避免地下降。随着芯片密度的增加，存储容量越来越大，需要更强大的纠错功能。因此，业界正迅速转向采用LDPC码，其可以提供比当前使用的码更大的纠错。然而，LDPC码具有高的解码复杂度，并且遭受错误平层问题，这阻止它们实现存储中所需的非常低的错误率。现有的LDPC解决方案使用复杂的后处理来处理错误平层问题，其代价是更多的功率和硬件，使得它们对于下一代SSD没有吸引力。使用基于迭代解码器故障分析的独特设计方法，将在硬件上开发和验证新的LDPC解决方案，以实现新兴存储器所需的目标可靠性增强，与最先进的解决方案相比，硬件和功耗降低10-20%。它们将专门进行优化，以满足企业SSD的可靠性需求。

The broader/commercial impacts of this this Small Business Innovation Research (SBIR) Phase I project are both technical and economic. The developed error-correction solutions will enable flash-memory-based devices to have higher capacities, higher reliability, and faster speeds at lower power while driving down the cost. This will have a major impact on mobile computing capabilities and enterprise storage by improving the efficiency and reliability of data centers, servers, and mission-critical storage that incorporate flash memories. Improved enterprise storage boosts the efficiency and growth of IT businesses, e-commerce, and financial trade. The solutions will also enable reduced power consumption and heat dissipation leading to greener systems, which is also a key driver for increased economic growth. From 2000 through 2012, the U.S. GDP has increased by 23.12% while energy consumption from all sources has increased by only 3.88% and this trend will be reinforced. The benefits of the error-correction solutions are also applicable to the hard disk drive and communications industries involving hundreds of billions of dollars in revenue and double digit growth rates.This Small Business Innovation Research Phase 1 project is related to the development of novel low-density parity-check (LDPC)-based error-correction for flash memory-based solid state drives (SSDs). While SSDs are rapidly gaining prominence especially in enterprise storage due to their high speeds, low power, and low heat dissipation, they face a major scaling problem as flash memory cell sizes must be shrunk to reduce their high cost, leading to an unavoidable degradation in the reliability. With a trend of increasing die density to enable higher storage capacities, more powerful error-correction is required. Therefore, the industry is swiftly moving towards adopting LDPC codes which can provide greater error-correction than the currently used codes. However, LDPC codes have a high decoding complexity and suffer from the error floor problem which prevents them from achieving very low error-rates needed in storage. Existing LDPC solutions use complex post-processing to deal with the error floor problem at the cost of more power and hardware making them unattractive for next generation SSDs. Using a unique design approach based on the analysis of iterative decoder failures, new LDPC solutions will be developed and validated on hardware that will achieve the target reliability enhancements needed for emerging memories, with a reduction of 10-20% in hardware and power compared to state-of-the art solutions. They will be optimized specifically to meet the reliability needs of enterprise SSD.