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SBIR Phase II: Low-density parity-check error correction for enhanced reliability of flash memories

SBIR Phase II: Low-density parity-check error correction for enhanced reliability of flash memories
SBIR 第二阶段:低密度奇偶校验纠错,增强闪存的可靠性
批准号:
1534760
负责人:
Shiva Planjery
金额:
$75.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2015
资助国家:
美国
项目状态:
已结题
起止时间:
2015-08-15 至 2022-06-30
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中文摘要
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英文摘要
The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project are both technical and economic. The developed error-correction solutions will enable flash-memory-based devices to have higher capacities, higher reliability, and faster speeds at lower power while driving down the cost. This will have a major impact on mobile computing capabilities and enterprise storage by improving the efficiency and reliability of data centers, servers, and mission-critical storage that incorporate flash memories. Improved enterprise storage boosts the efficiency and growth of IT businesses, e-commerce, and financial trade. The solutions will also enable reduced power consumption and heat dissipation leading to greener systems. The benefits of the error-correction solutions are also applicable to the hard disk drive and communications industries.This Small Business Innovation Research (SBIR) Phase II project will develop and validate novel low-density parity-check (LDPC)-based error-correction for flash memory-based solid state drives (SSDs). SSDs are rapidly being deployed for both enterprise and consumer storage due to their fast speeds, low power, and low heat dissipation. But they bring numerous technical challenges stemming from the fact that reducing flash memory cell sizes leads to an unavoidable degradation in the reliability. With a trend of increasing die density to enable higher storage capacities, the industry is swiftly moving towards adopting LDPC codes to provide more powerful error-correction. However existing LDPC solutions use complex post-processing and multiple reads to bring down the error rates to the desired levels which lowers the read speeds, making them unattractive for future SSDs. Novel binary LDPC-based solutions will be developed for a range of parameters, and validated in hardware. The design method will be extended to develop new non-binary LDPC solutions which provide even greater reliability enhancements, leading to greater endurance in SSDs.
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  • 批准号:
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