Collaborative Research: Computational Study of Low Volume Solder Interconnects for 3D Integrated Circuit Packaging

摩尔定律预测，集成电路中的晶体管数量大约每两年翻一番，几十年来一直是美国经济的主要驱动力。不幸的是，与不断缩小的设备相关的技术和根本性挑战使目前的进步速度不可持续。最近，3D集成电路技术已经成为一种领先的方法，通过堆叠芯片而不是缩小设备尺寸来遵守摩尔定律。为了实现3D集成，必须开发用于互连和叠层键合的新的连接技术。由于其良好的电学、热学和机械性能，采用低容量焊料互连进行键合特别有前景。该合作研究奖支持基础研究，以获得开发低容量焊料互连所需的知识。研究成果不仅将有助于实现这种新的键合技术在3D集成电路封装中的全部潜力，而且还将用于改进在航空航天和核电行业以及电力电子和热管理应用中重要的连接方法。此外，该项目将有助于在两个代表不足的群体之间建立有效的合作。小尺寸的焊料互连使焊点可以通过形成金属间化合物等温凝固，而不是以液体焊料为代价。这种技术也称为瞬时液相键合，允许在低于预期工作条件的温度下形成接头，将过热对电路的温度敏感元件的损害降至最低。然而，小体积焊料互连的小尺寸导致了工作过程中的大电流密度。这些大电流密度会产生很大的电、热和机械驱动力，从而导致复杂的微结构过程。这项研究旨在促进对小体积焊料互连中复杂的微结构过程的基本理解，特别是对控制processing-microstructure-property-performance关系的重要微观机制的理解。该研究小组将开发一种集成的多物理相场模型，并对低容量焊料互连的加工、操作和损坏过程中的微结构形成和演变进行系统的模拟研究。这些模拟将用于将宏观工艺参数和操作条件与微观现象相关联，包括扩散、电流流动、热传递和应力集中，并阐明缺陷形成的机理。

Moore's Law, which predicts that the number of transistors in an integrated circuit doubles approximately every two years, has been a major driver for the US economy for decades. Unfortunately, technological and fundamental challenges associated with continued device shrinking make the current rate of progress unsustainable. Recently, 3D integrated circuit technology has emerged as a leading approach to keep up with Moore's Law by stacking chips rather than by shrinking device dimensions. To achieve 3D integration, new joining technologies for interconnection and stacked bonding must be developed. Bonding by low volume solder interconnects is specially promising due to their good electrical, thermal, and mechanical properties. This collaborative research award supports fundamental research to obtain the knowledge needed for the development of low volume solder interconnects. Research results will not only help realize the full potential of this new bonding technique in 3D integrated circuit packaging, but also be used to improve joining methodologies important in the aerospace and nuclear power industries and in power electronics and thermal management applications. Moreover, the project will help establish an effective collaboration between the two PIs who are both from underrepresented groups.The small dimensions of low volume solder interconnects make it possible for the solder joints to solidify isothermally through the formation of intermetallic compounds at the expense of the liquid solders. This technique, also known as Transient Liquid Phase Bonding, allows the formation of a joint at temperatures lower than the expected operating conditions, minimizing damage to the temperature-sensitive components of the circuits from overheating. However, the small dimensions of low volume solder interconnects lead to large current densities during operation. These large current densities induce large electrical, thermal, and mechanical driving forces which give rise to complex microstructural processes. This research aims to advance the fundamental understanding of the complex microstructure processes in low volume solder interconnects, in particular about the important microscopic mechanisms governing processing-microstructure-property-performance relationships. The research team will develop an integrated multi-physics phase field modeling and perform systematic simulation studies of the microstructure formation and evolution during processing, operation, and damage of low volume solder interconnects. The simulations will be used to correlate macroscopic processing parameters and operating conditions to microscopic phenomena involving diffusion, current flow, heat transfer and stress concentration, and elucidate the mechanisms of defect formation.