Large-Scale Fabrication of Multi-Nanopillar Transistors for Energy-Efficient Electronics

一项能够大幅降低电子设备运行能耗的技术将有望在商业、军事和空间领域得到广泛应用。例如，智能手机、笔记本电脑和平板电脑的能耗降低十倍，电池充电频率也会降低十倍。然而，由于当前电子器件通常使用的晶体管架构的限制，获得器件能耗的这种降低一直是具有挑战性的。该奖项将研究一种新的晶体管技术，其中晶体管组件在单个纳米级支柱内制造，其工作原理允许电子以非常小的能量消耗流动。该项目的成功实施将使家庭、办公室、商店、机场等电子系统的能源消耗大幅减少，这将有利于美国的经济、环境和社会。预计还将带来各种军事利益，例如士兵在执行任务时携带的重量轻、能效更高的电子设备，提高他们的作战能力，增强我们国家在国内外的安全。现代电子设备的大规模集成电路中的大量能量消耗或热耗散是抑制电子设备技术进步的关键问题。其根本原因是电子的热激发，这对实现陡峭的ON/OFF切换施加了限制，导致大量的能量消耗。本项目研究了一种新的晶体管，其中电子热激发被有效地抑制，以便可以在室温下获得陡峭的ON/OFF开关能力，从而大幅降低晶体管操作中的能耗。晶体管将被构造为单个纳米柱，每个纳米柱包含所有晶体管组件，例如源极、量子阱、隧穿势垒、半导体岛和漏极。量子阱中的离散态将充当能量过滤器，其阻挡高能电子的传输并有效地抑制电子热激发。重要的是，纳米柱晶体管将大规模制造，结合CMOS兼容的并行工艺和利用自限制静电纳米颗粒放置技术的纳米颗粒的自下而上组装，其中纳米颗粒用作用于生产可单独寻址的纳米柱的蚀刻硬掩模。

A technology that enables substantial reduction of energy consumption in the operation of electronic devices would promise numerous commercial, military and space applications. For example, ten-fold reduction of energy consumption for smart phones, laptops and tablets could result in ten-fold reduction in frequency of battery recharging. However, obtaining such reductions in device energy consumption has been challenging due to limitations of the transistor architecture that current electronic devices commonly use. This award will investigate a new transistor technology in which the transistor components are made within a single nanoscale pillar and whose operating principle allows electrons to flow with very little energy consumption. A successful execution of this project will enable significant reductions in energy consumption by electronic systems at home, office, store, airport, etc., which will benefit the U.S. economy, environment and society, in general. Various military benefits are also expected, such as, lightweight, more energy-efficient electronic equipment that soldiers carry in their missions, increasing their combat capabilities, enhancing the security of our nation at home and abroad. A large amount of energy consumption or heat dissipation in the large-scale integrated circuits of modern electronic devices is a critical problem that inhibits the advancement of electronic device technology. Its root cause is the thermal excitation of electrons, which imposes limitations on enabling steep ON/OFF switching, resulting in a large amount of energy consumption. This project investigates a new transistor in which the electron thermal excitation is effectively suppressed so that steep ON/OFF switching capability can be obtained at room temperature, leading to substantial reduction of energy consumption in the transistor operation. The transistors will be constructed as single nanopillars, with each nanopillar containing all the transistor components, such as source, quantum well, tunneling barrier, semiconductor island and drain. A discrete state in the quantum well will serve as an energy filter, which blocks the transport of energetic electrons and effectively suppresses the electron thermal excitation. Importantly, the nanopillar transistors will be fabricated on a large scale combining CMOS-compatible parallel processes and bottom-up assembly of nanoparticles that utilizes self-limiting electrostatic nanoparticle placement technique, where the nanoparticles are used as etch hard masks for producing individually addressable nanopillars.