SBIR Phase I: Area and Energy Efficient Error Floor Free Low-Density Parity-Check Codes Decoder Architecture for Flash Based Storage

这个小企业创新研究（SBIR）第一阶段项目的更广泛的影响/商业潜力将是一个比现在更有效和高效的闪存纠错方案。这将提供更好的可靠性和延长闪存的寿命，并将对一些技术和市场产生重大影响，如数据中心的企业存储、固态驱动器、平板电脑、智能手机和其他消费电子产品。据估计，2013年闪存市场的生产和销售额为301亿美元，预计到2018年将增长到439亿美元。据估计，2014年企业存储市场规模将达到10亿美元，并有望在未来几年保持强劲增长。这个市场的很大一部分与闪存的纠错控制器有关，考虑到闪存的快速缩小和容量的增加带来了比以前更多的读取错误，这一目标比以往任何时候都更加重要。这个小企业创新研究（SBIR）第一阶段项目将解决和开发工具，以克服传统上阻碍低密度奇偶校验（LDPC）代码部署在闪存和纠错控制器中的问题。一个主要的问题是，这些代码有错误层，这使它们无法达到闪存所需的非常低的错误概率。为了克服这一缺陷，将开发新的算法来理解问题的本质，并使用先进的信号处理方法来消除它。将开发面积和能源效率高的解码器技术，使LDPC码适用于闪存应用。这将包括研究优化基于LDPC的误差校正系统，以提高面积和能源效率，并消除误差地板问题。它还将包括优化详细电路设计的研究。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project will be a substantially more effective and efficient error correction scheme for flash memory than exists today. This will provide better reliability and extend the life of flash memory and will have a major impact on several technologies and markets such as enterprise storage at data centers, solid state drives, tablets, smart phones, and other consumer electronics. The flash memory market was estimated to include $30.1 billion in production and sales in 2013 and is expected to grow to $43.9 billion by 2018. The enterprise storage market is estimated to be $1 billion in 2014 and a robust growth is expected over the next few years. A substantial fraction of this market is related to error correction controllers for flash memories which are playing an even more important goal than ever considering the rapid scaling down and increasing capacities of flash memories which introduce more read errors than before.This Small Business Innovation Research (SBIR) Phase I project will address and develop tools to overcome problems that have traditionally prevented low-density parity-check (LDPC) codes from being deployed in flash memories and error correction controllers. A major problem is that these codes have error floors which prevent them from achieving very low error probabilities required in flash memories. In order to overcome this deficiency, new algorithms will be developed to understand the nature of the problem and to eliminate it using advanced signal processing methods. Area and energy efficient decoder technologies will be developed that make LDPC codes suitable for flash applications. This will include research optimizing LDPC based error correction systems for area and energy efficiency and elimination of the error floor problem. It will also include research on optimizing the detailed circuit design.