SBIR Phase II: Area and Energy Efficient Error Floor Free Low-Density Parity-Check Codes Decoder Architecture for Flash Based Storage

SBIR 第二阶段：用于基于闪存的存储的面积和能源效率高、无错误层的低密度奇偶校验码解码器架构

• 批准号: 1632562
• 负责人: Paul Budnik
• 金额: $ 75万
• 依托单位: TexasLDPC Inc., dba Symbyon Systems
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2016
• 资助国家: 美国
• 起止时间: 2016-09-01 至 2019-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1632562&HistoricalAwards=false
• 关键词: SBIR; Phase; II; Area; Energy

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project will be high performance error correction for flash memory. Error correction plays a critical row in making digital devices reliable. Shrinking semiconductor geometries results in more errors. This has created a special problem for flash memory where the need for more rigorous error correction is approaching a practical limit with the widely used Bose Chaudhuri Hocquengham error correction. Low Density Parity Check (LDPC) is a recognized solution that can approach the theoretical limits of what is possible. This LDPC based technology can improve lifetime of flash by without the added cost of the existing BCH solution. This technology helps Flash Memory enterprises to use higher density flash to improve storage capacity and cut the storage product costs. Without the superior performance, small size and low power consumption of the LDPC technology, the migration to low cost high capacity flash memories will be seriously slowed. In the absence of a comparable alternative approach, there will be serious limitations on the performance of a vast array of products that depend on highly reliable and economical flash storage.This Small Business Innovation Research (SBIR) Phase II project will use a variety of techniques to minimize the area and power requirements and enhance the performance of Low Density Parity Check (LDPC) error correction codes for flash memory. Many of these techniques are applicable to a wide range of error correction applications in digital communication and storage from WiFi to hard disk drives. The need for better error correction is crucial for flash memory but there is a widening demand for improved error correction. For example larger memories require better error correction to insure the system failure rate is low. In the next two years the company expects to develop a Verilog version of the LDPC decoder that is easily integrated with a flash controller. The project will work with potential customers/partners to ensure the code works with controllers. In the long run these techniques can be adapted to a wide range of applications as the need for more reliable data continues to rapidly expand.

该小型企业创新研究 (SBIR) 第二阶段项目的更广泛影响/商业潜力将是闪存的高性能纠错。纠错对于数字设备的可靠性至关重要。缩小半导体几何形状会导致更多错误。这给闪存带来了一个特殊的问题，对于更严格的纠错的需求已经接近广泛使用的 Bose Chaudhuri Hocquengham 纠错的实际极限。低密度奇偶校验 (LDPC) 是一种公认​​的解决方案，可以接近可能的理论极限。这种基于 LDPC 的技术可以延长闪存的使用寿命，而无需增加现有 BCH 解决方案的成本。该技术帮助闪存企业使用更高密度的闪存来提高存储容量并降低存储产品成本。如果没有LDPC技术的优越性能、小尺寸和低功耗，向低成本大容量闪存的迁移将会严重减慢。如果没有类似的替代方法，依赖于高度可靠和经济的闪存存储的大量产品的性能将受到严重限制。这个小型企业创新研究（SBIR）第二阶段项目将使用各种技术来最大限度地减少面积和功耗要求，并增强闪存低密度奇偶校验（LDPC）纠错码的性能。其中许多技术适用于从 WiFi 到硬盘驱动器的数字通信和存储中的广泛纠错应用。更好的纠错能力对于闪存至关重要，但对改进纠错能力的需求也在不断扩大。例如，较大的存储器需要更好的纠错以确保系统故障率较低。该公司预计在未来两年内开发出可轻松与闪存控制器集成的 LDPC 解码器的 Verilog 版本。该项目将与潜在客户/合作伙伴合作，以确保代码适用于控制器。从长远来看，随着对更可靠数据的需求不断迅速扩大，这些技术可以适应广泛的应用。