SBIR Phase II: Area and Energy Efficient Error Floor Free Low-Density Parity-Check Codes Decoder Architecture for Flash Based Storage

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The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project will be high performance error correction for flash memory. Error correction plays a critical row in making digital devices reliable. Shrinking semiconductor geometries results in more errors. This has created a special problem for flash memory where the need for more rigorous error correction is approaching a practical limit with the widely used Bose Chaudhuri Hocquengham error correction. Low Density Parity Check (LDPC) is a recognized solution that can approach the theoretical limits of what is possible. This LDPC based technology can improve lifetime of flash by without the added cost of the existing BCH solution. This technology helps Flash Memory enterprises to use higher density flash to improve storage capacity and cut the storage product costs. Without the superior performance, small size and low power consumption of the LDPC technology, the migration to low cost high capacity flash memories will be seriously slowed. In the absence of a comparable alternative approach, there will be serious limitations on the performance of a vast array of products that depend on highly reliable and economical flash storage.This Small Business Innovation Research (SBIR) Phase II project will use a variety of techniques to minimize the area and power requirements and enhance the performance of Low Density Parity Check (LDPC) error correction codes for flash memory. Many of these techniques are applicable to a wide range of error correction applications in digital communication and storage from WiFi to hard disk drives. The need for better error correction is crucial for flash memory but there is a widening demand for improved error correction. For example larger memories require better error correction to insure the system failure rate is low. In the next two years the company expects to develop a Verilog version of the LDPC decoder that is easily integrated with a flash controller. The project will work with potential customers/partners to ensure the code works with controllers. In the long run these techniques can be adapted to a wide range of applications as the need for more reliable data continues to rapidly expand.