Architecture Support for Advancing PGAS (ASAP)

对于程序员来说，并行计算机和现代多核处理器芯片的体系结构正变得相当复杂，这些芯片包含数十个甚至最终数百个处理器。这些系统的有效编程对于在降低功耗的同时实现高速处理是非常重要的。要做到这一点，程序员必须确保：1.程序中的工作被分解为尽可能多的并行活动，以实现快速处理；2.数据位于靠近处理核心的位置，这些处理核心将对它们进行操作，以避免数据在系统中传输的时间较长，从而损失更多时间和精力。编程模型是一种抽象，它为程序员提供了一个易于使用的逻辑视图，隐藏了底层系统的复杂性，同时促进了高效的编程。这是两个相互冲突的需求，虽然当前的实际编程方法可以在大多数情况下提供效率，但它们并不容易使用。所谓的PGAS或分区全局地址空间编程模型有望在效率和易用性之间取得平衡。然而，需要来自硬件的帮助，特别是在简化和加快查找要处理的数据的物理位置的过程方面。本文的工作就是在PGAS编程模型下研究该问题的硬件解决方案。这一成果将提高领域科学家的生产力，从而减少从构思应用程序问题到获得解决方案的时间，从长远来看，这意味着更快的发现和创新，以及开发下一代软件的成本降低。PI建议研究用于PGAS编程模型的地址转换的通用硬件支持。PGA在位置感知但显式的消息传递模型(例如MPI)和易于使用但与位置无关的共享内存模型(例如OpenMP)之间取得了平衡。然而，PGAS富内存模型以性能为代价，这可能会阻碍其可伸缩性和性能的潜力。与访问其私有空间相比，当前的实现在访问本地共享空间方面可能要慢一个数量级。编译器优化只处理特殊情况，手动调优使得PGAS的易用性优势变得毫无价值。建议的硬件解决方案可以促进开箱即用(即非手动调整)的PGAS应用程序的高性能执行。PI正在创建PAG内存模型转换体系结构支持，它可以动态高效地导航PGAS内存模型，将PGAS共享引用转换为系统的虚拟地址。这消除了手动调优的需要，同时保持了PGAS语言的性能和生产力。编译器将通过指令集扩展获得硬件支持。将现有的微体系结构仿真器与编译器和运行时系统集成并适配的工具集将作为主要的测试床，并分布在集群上进行广泛的实验。在项目结束时，投资促进机构希望发布在该项目下使用的工具和基准。

Architectures of parallel computers and modern manycore processor chips, that contain tens and eventually hundreds of processors, are becoming quite complex for the programmers. Efficient programming of those systems is very important to achieve high-speed of processing while reducing power. To do so, programmers must ensure that: 1. the work in the program is broken into as many parallel activities as possible for fast processing; 2. data is located close to the processing cores that will manipulate them to avoid making the data travel long in the system thereby losing more time and wasting energy. Programming models are abstractions that provide the programmer with an easy-to-use logical view that hides the complexity of the underlying systems, while facilitating efficient programming. These are two conflicting requirements and while the current de facto programming methods can offer efficiency in the majority of the cases, they are not easy to use. The so called, PGAS or the Partitioned Global Address Space programming model has the promise of striking a balance between efficiency and ease-of-use. However, help is needed from the hardware particularly in simplifying and speeding up the process of finding where the data to be processed is physically located. This work is to investigate hardware solutions for this problem under the PGAS programming model. The outcome will improve productivity of domain scientists, thereby reducing the time from conceiving an application problem till the solution is attained, which in the long run can mean more rapid discoveries and innovations, as well reduction in the cost of developing the next generation software. The PIs propose to investigate a general hardware support for address translation for the PGAS programming model. PGAS strikes a balance between the locality-aware, but explicit, message-passing model (e.g. MPI) and the easy-to-use, but locality-agnostic, shared memory model (e.g. OpenMP). However, the PGAS rich memory model comes at a performance cost which can hinder its potential for scalability and performance. Current implementations can be orders of magnitude slower in accessing local shared space as compared to accessing their private space. Compiler optimizations only handle special cases and hand-tuning renders the PGAS ease-of-use advantage worthless. The proposed hardware solution can facilitate high-performance execution for out-of-the-box (i.e. non-hand-tuned) PGAS applications. The PIs are creating PAGS memory model translation architectural support, which can navigate the PGAS memory model converting PGAS shared references to system's virtual addresses efficiently on-the-fly. This eliminates the need for hand-tuning, while maintaining the performance and productivity of PGAS languages. The hardware support will be available to the compiler through instruction set extensions. A tool set integrating and adapting existing micro-architecture simulators with compiler and a run-time system will be used as the main testbed and distributed over a cluster for extensive experimentation. At the end of the project the PIs expect to release tools and the benchmarks utilized under this project.