EAGER: Designing Novel Polymorphic Gates as Hardware Security Primitives

传统的数字逻辑门将为给定的一组输入信号（称为输入向量）生成确定性的输出信号。多态门的不同之处在于，它们对于相同输入向量的输出可以根据操作环境（例如温度、电压和湿度）而变化。因此，我们可以把多态门看作是一种逻辑门，它可以实现多种功能，并根据某些可控因素表现为其中之一。这是因为多态栅极在晶体管级具有非常规结构。然而，这种非常规的结构很难找到，因为它已经被研究人员证明，因为这个概念是由NASA的研究人员在2001年提出的，以尽量减少设计的芯片面积。在这个EAGER项目中，我们建议研究系统的方法来构建物联网（IoT）和网络安全应用的新型多态门。这个项目将集中在三个使能技术的发展，建立多态门作为硬件安全原语。首先，由于多态门是罕见的，研究人员如何构建足够的类型，以便我们可以将它们集成到传统的CMOS技术以及新的纳米技术？我们将通过研究部分多态门的新概念和相关的进化算法来找到实现这种多态门的晶体管结构来回答这个问题。第二，什么样的安全应用程序可以从多态门中受益？我们建议在几个具体的网络安全应用中，如知识产权保护、电路混淆、设备认证和随机数生成，展示多态门作为硬件安全原语的巨大潜力。第三，基于多态门的安全性有多好？我们将对提出的安全应用程序进行理论和实证分析，并提供适当的攻击模型和潜在的对策。EAGER项目的任何成功都将是对多态门及其应用、硬件安全、进化算法、器件物理和电路理论感兴趣的研究界的革命。

Conventional digit logic gates will generate a deterministic output signal for a given set of input signals (called input vector). Polymorphic gates are different in the sense that their output for the same input vector may vary depending on the operating environment such as temperature, voltage, and humidity. So we can consider polymorphic gates as logic gates that can implement multiple functions and behave as one of them according to certain controllable factors. This happens because polymorphic gates have unconventional structure at the transistor level. However, such unconventional structure is hard to find as it has been demonstrated by researchers since this concept was proposed by NASA researchers in 2001 in an effort to minimize chip area of the design. In this EAGER project, we propose to investigate systematic methods to construct novel polymorphic gates for Internet of Things (IoT) and cybersecurity applications. This project will focus on the development of three enabling technologies to establish polymorphic gates as a hardware security primitive. First, since polymorphic gates are rare, how can researchers construct sufficient types of them so we can integrate them into the conventional CMOS technology as well as new nano-technology? We will answer this question by studying the novel concept of partial polymorphic gates and the associated evolutionary algorithms to find the transistor structure that implements such polymorphic gates. Second, what security applications can benefit from the polymorphic gates? We propose to demonstrate the great promise of polymorphic gates as a hardware security primitive on several concrete cybersecurity applications, such as intellectual property protection, circuit obfuscation, device authentication, and random number generation. Third, how good is polymorphic gates based security? We will conduct both theoretical and empirical analysis on the proposed security applications with proper attack models and potential countermeasures. Any success from this EAGER project will be revolutionary to the research community that is interested in polymorphic gates and their applications, hardware security, evolutionary algorithms, device physics and circuit theory.