SBIR Phase I: Processor Architecture for Radically Improved Performance and Energy Efficiency on Sparse Machine Learning

这个小企业创新研究（SBIR）第一阶段项目的更广泛的影响/商业潜力是扩展现代计算机系统执行机器学习应用程序的能力，并使机器学习在人们的日常生活中有新的用途。由于广泛的成功，机器学习正在被应用于大多数现代企业的自动化任务。然而，这些新问题的计算复杂性和数据密集性正在迅速增加。当前问题的规模强调了现代系统的计算能力和内存要求。在第一阶段项目下开发的技术将使计算机系统在执行这些机器学习任务时具有更高的性能和能源效率。高效的机器学习将使复杂的任务能够适应现代移动设备，同时使数据中心内的计算机能够解决越来越大的问题。最后，随着企业急于为机器学习部署硬件，底层算法和技术也在迅速发展。该技术具有很强的适应性，既能提高现有机器学习技术的效率，又能降低企业可能采用新机器学习算法的风险。提议的项目引入了一种新的硬件架构，用于执行数据和控制密集的机器学习工作负载。随着机器学习的使用范围扩大，数据量的增加带来了压缩数据表示的使用。然而，由于不规则的控制和数据访问模式，现代计算设备（如微处理器或图形处理器）在使用这些压缩表示处理问题时效率非常低。这个阶段I项目引入了一个适应性强的体系结构，它擅长于不规则计算，并且可以动态地重新分配资源以加速执行。为了展示新架构的功能，将对现代机器学习应用程序中的关键执行内核进行调整和开发，以在压缩表示上运行。现有的模拟基础设施将扩展到模拟关键硬件需求，并收集新提出的硬件架构的性能评估。初步估计表明，在机器学习应用的关键操作中，能源效率和性能的改善有多种因素。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to expand the capability of modern computer systems to execute machine learning applications and enable new uses of machine learning in the everyday lives of people.  Due to widespread success, machine learning is being applied to automate tasks across most modern businesses.  However, the increasingly computationally complex and data intensive nature of these new problems is rapidly increasing. The scale of current problems stress the computational abilities and memory requirements of modern systems.  The technology to be developed under this Phase I project, will enable computer systems with radically higher performance and energy-efficiency while performing these machine learning tasks.  Enabling efficient machine learning will enable complex tasks to fit within modern mobile devices while simultaneously enabling computers within datacenters to solve increasingly large problems.  Finally, as businesses rush to deploy hardware for machine learning, the underlying algorithms and techniques are rapidly evolving.  The technology to be developed is highly adaptable, enabling high efficiency on current machine learning techniques while mitigating risks for businesses likely to adapt new machine learning algorithms.The proposed project introduces a new hardware architecture for the execution of data and control intensive machine learning workloads.  As machine learning has expanded in use, increasing data sizes have brought about the use of compressed data representations.  However, modern computational devices like microprocessors or graphics processors are highly inefficient when working on problems using these compressed representations due to irregular control and data access patterns.  This Phase I project introduces an adaptable architecture that excels at irregular computing and can dynamically re-allocate resources to hasten execution.  To demonstrate the capabilities of the new architecture, key execution kernels from modern machine learning applications will be adapted and developed to operate on compressed representations.  An existing simulation infrastructure will be extended to model key hardware requirements and gather performance estimations of the newly proposed hardware architectures.  Preliminary estimates demonstrate that multiple factors of improvement in energy efficiency and performance are expected across the key operations of machine learning applications.