FoMR: Secure, Light-Weight Speculative Engines for Coordinated and Cohesive Speculation in Future Memory Systems

由于几十年来以同样的成本在一个给定的区域内封装更多处理器的趋势放缓，计算机系统的规模在未来十年提出了一个巨大的挑战。在这个新时代，改进制造工艺的好处将在很大程度上消失。因此，必须通过处理器设计的进步来赢得处理器的性能。本研究的目标是开发安全技术，通过准确推测未来的内存引用和数据值来提高处理器性能。在高层次上，该研究利用轻量级推测引擎，推测程序路径和数据值，而没有完整核心的开销，预测引用模式和推测读/写集，以减轻对指令级并行（ILP）提取的内存延迟影响。该项目解决了对新架构技术的关键需求，这些技术可以安全地提高功率效率和ILP。此外，随着计算机行业努力吸引具有应对这些挑战的技能的人才，该项目解决了各级计算机工程师对高效，安全处理器设计的理解的需求。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The scaling of computer systems through the next decade poses a grand challenge due to the slowing down of the decades-long trend of packing more processors into a given area at the same cost. In this new era, the benefits of improved manufacturing processes will largely end. Thus, processor performance must be won through processor design advancement. The goal of this research is to develop secure techniques to improve processors performance by accurately speculating on future memory references and data values. At a high level the research leverages light-weight speculation engines, speculating on program path and data values without the overheads of a full core, predicting reference patterns and speculating on read/write sets to alleviate memory latency effects on instruction-level parallelism (ILP) extraction. This project addresses a critical need for new architectural techniques which securely improve both power efficiency and ILP. Furthermore, this project addresses the need for computer engineers at all levels with an understanding of efficient, secure processor design, as the computer industry struggles to attract talent with the skills to meet these challenges.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.