SBIR Phase I: Energy Efficient Neural Network Accelerator Featuring a Logic Compatible Non-Volatile Synapse Array

这个小型企业创新研究（SBIR）第一阶段项目的更广泛的影响/商业潜力是加速物联网和移动的设备中人工智能功能的采用。 所提出的基于多位非易失性存储器（NVM）的深度神经网络（DNN）IP基于标准CMOS逻辑工艺。DNN硬件的现有解决方案通常需要片外访问以从外部存储器检索神经网络参数，从而导致额外的通信延迟和功耗。此外，当关键的神经网络参数在芯片外传输时，可能会出现安全或隐私问题，这对于诸如个性化AI设备之类的应用来说是不可接受的。在特殊的NVM工艺中集成DNN引擎的替代方法需要超过常规逻辑CMOS工艺的多达10个额外的掩模，这对于成本敏感的边缘器件中的中等密度DNN引擎来说是不具有成本效益的。有了这个IP，任何需要持久人工智能功能的现有或新的片上系统都可以快速、经济高效地构建。这个小型企业创新研究（SBIR）第一阶段项目旨在为边缘设备开发一个经济高效的非易失性神经网络加速器IP。为了解决与传统方法相关联的安全性、延迟、功耗和成本问题，提出了基于单多晶硅的低成本、非易失性、多位eFlash单元。然而，由于信噪比的固有降低，多位单元操作提出了重大挑战。关键的技术障碍包括解决干扰的MEMS单元，提高感测裕度，并克服与读出电路中的高电压操作相关的可靠性问题，以及开发鲁棒的神经网络单元阵列。为了应对这些挑战，已经提出了与多位单元、高压电路和单元编程方法相关的若干新想法。一旦在该项目中成功验证，多位单元IP就可以集成为逻辑兼容非易失性存储器，以在芯片上存储神经网络参数，或者集成为逻辑兼容非易失性神经网络IP，以执行整个神经网络操作。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to accelerate the adoption of AI features in Internet of Things and mobile devices. The proposed multi-bit non-volatile memory (NVM) based Deep Neural Networks (DNN) IP is based on the standard CMOS logic processes. Existing solution for the DNN hardware typically requires off-chip access to retrieve neural network parameters from external memories, incurring additional communication latency and power consumption. Additionally, when critical neural network parameters are transmitted off-chip, security or privacy concern may arise, which is unacceptable especially for the applications such as personalized AI devices. Alternative approach integrating the DNN engine in a special NVM process requires as much as 10 additional masks beyond the conventional logic CMOS process which is not cost-effective for medium density DNN engine in cost-sensitive edge devices. With this proposed IP, any existing or new system on chip requiring persistent AI functionality can be built quickly and cost effectively.This Small Business Innovation Research (SBIR) Phase I project seeks to develop a cost-effective non-volatile neural network accelerator IP for edge devices. To solve the security, latency, power consumption, and cost issues associated with the traditional approaches, a single-poly based low cost, non-volatile, multi-bit eFlash cell is proposed. Multi-bit cell operation however presents significant challenges due to inherent reduction in signal-to-noise ratio. Key technical hurdles include solving disturbances of unselected cells, improving sensing margin, and overcoming reliability issues associated with high voltage operation in readout circuits as well as developing robust neural network cell arrays. To address these challenges, several new ideas related to multi-bit cell, high-voltage circuits, and cell programming methods have been proposed. Once verified successfully in this project, the multi-bit cell IP can then be integrated as logic compatible non-volatile memory to store neural network parameters on-chip, or as logic compatible non-volatile neural network IP to execute entire neural network operation.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.