SBIR Phase II: Logic compatible non-volatile neural network accelerator using analog compute-in-memory architecture

小型企业创新研究(SBIR)第二阶段项目的更广泛影响/商业潜力是启用能够在本地运行神经网络的高能效智能物联网(IoT)设备。拟议的高能效神经网络加速器解决方案使用电路架构，允许芯片面积较小，这是在移动设备等空间受限的系统中采用和包含成本效益的关键推动因素。与现有的基于数字逻辑的加速器解决方案相比，该解决方案是节能的，这将使EDGE实施适用于功率受限的系统。在几乎所有制造铸造厂的先进标准逻辑流程中，制造流程都是完全可扩展的，因此允许广泛采用该架构。该项目的成果将是一个高能效的片上系统(SoC)解决方案，在无需云访问的情况下在智能物联网设备中提供人工智能集成，同时实现安全和隐私增强。该小型企业创新研究(SBIR)第二阶段项目旨在进一步开发一种节能的模拟电路拓扑和容忍变化的系统解决方案。为了在先进的半导体工艺技术中实现基于模拟内存计算架构的神经网络加速器解决方案，需要在降低电源电压和噪声容限的情况下解决重大的设计挑战。结合最新提出的面积高效和性能高效的模拟内存计算架构解决方案，将通过该项目在先进的工艺技术中设计、制造和验证逻辑兼容的非易失性神经网络加速器知识产权核。一旦在该项目中成功地从制造的硅中验证，建议的神经网络IP将准备作为未来人工智能系统的关键构建块集成在芯片上，并实现节能的智能边缘物联网设备。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is to enable energy efficient smart internet of things (IoT) devices capable of running a neural network locally. The proposed energy-efficient neural network accelerator solution uses circuit architecture that allows for chips with a small area, a key enabler for cost-effective adoption and inclusion in space-constrained systems such as mobile devices. The solution is energy-efficient compared to the existing digital logic-based accelerator solutions, which will enable edge implementation for systems with power constraints. The manufacturing process is fully scalable in advanced standard logic processes at almost all manufacturing foundries, thus allowing for widespread adoption of the architecture. The outcome of this project will be an energy-efficient system on a chip (SoC) solution that offers artificial intelligence integration in smart IoT devices without cloud access, while enabling security and privacy enhancements. This Small Business Innovation Research (SBIR) Phase II project seeks to further develop an energy efficient analog circuit topology and variation tolerable system solution. To enable analog compute-in-memory architecture based neural network accelerator solution in an advanced semiconductor process technology, significant design challenges need to be solved with reduced supply voltage and noise margin. Along with the newly proposed area efficient and performance efficient analog compute-in-memory architecture solution, the logic compatible non-volatile neural network accelerator intellectual property core will be designed, fabricated, and validated in the advanced process technology through the project. Once verified successfully from the fabricated silicon in this project, the proposed neural network IP will be ready to be integrated as a key building block of future artificial intelligence systems on a chip and enable energy-efficient smart edge IoT devices.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.