课题基金 / 基金详情

SBIR Phase II: Logic compatible non-volatile neural network accelerator using analog compute-in-memory architecture

SBIR Phase II: Logic compatible non-volatile neural network accelerator using analog compute-in-memory architecture
SBIR 第二阶段:使用模拟内存计算架构的逻辑兼容非易失性神经网络加速器
批准号:
1951113
负责人:
Seung-Hwan Song
金额:
$75.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2020
资助国家:
美国
项目状态:
未结题
起止时间:
2020-05-01 至 2025-08-31

项目摘要

项目成果

Seung-Hwan Song的其他基金

相似基金

相关文献

中文摘要
翻译
点击翻译按钮获取中文摘要
英文摘要
The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is to enable energy efficient smart internet of things (IoT) devices capable of running a neural network locally. The proposed energy-efficient neural network accelerator solution uses circuit architecture that allows for chips with a small area, a key enabler for cost-effective adoption and inclusion in space-constrained systems such as mobile devices. The solution is energy-efficient compared to the existing digital logic-based accelerator solutions, which will enable edge implementation for systems with power constraints. The manufacturing process is fully scalable in advanced standard logic processes at almost all manufacturing foundries, thus allowing for widespread adoption of the architecture. The outcome of this project will be an energy-efficient system on a chip (SoC) solution that offers artificial intelligence integration in smart IoT devices without cloud access, while enabling security and privacy enhancements. This Small Business Innovation Research (SBIR) Phase II project seeks to further develop an energy efficient analog circuit topology and variation tolerable system solution. To enable analog compute-in-memory architecture based neural network accelerator solution in an advanced semiconductor process technology, significant design challenges need to be solved with reduced supply voltage and noise margin. Along with the newly proposed area efficient and performance efficient analog compute-in-memory architecture solution, the logic compatible non-volatile neural network accelerator intellectual property core will be designed, fabricated, and validated in the advanced process technology through the project. Once verified successfully from the fabricated silicon in this project, the proposed neural network IP will be ready to be integrated as a key building block of future artificial intelligence systems on a chip and enable energy-efficient smart edge IoT devices.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
期刊论文(0)
专著(0)
科研奖励(0)
会议论文
SBIR Phase I: Energy Efficient Neural Network Accelerator Featuring a Logic Compatible Non-Volatile Synapse Array
  • 批准号:
    1843483
  • 项目类别:
    Standard Grant
  • 资助金额:
    $22.49万
  • 财政年份:
    2019
  • 负责人:
    Seung-Hwan Song
  • 依托单位:
国内基金
海外基金
Baryogenesis, Dark Matter and Nanohertz Gravitational Waves from a Dark Supercooled Phase Transition
  • 批准号:
    24ZR1429700
  • 项目类别:
    省市级项目
  • 资助金额:
    --
  • 批准年份:
    2024
  • 负责人:
    YUICHIRO NAKAI
  • 依托单位:
ATLAS实验探测器Phase 2升级
  • 批准号:
    11961141014
  • 项目类别:
    国际(地区)合作与交流项目
  • 资助金额:
    3350万元
  • 批准年份:
    2019
  • 负责人:
    刘衍文
  • 依托单位:
地幔含水相Phase E的温度压力稳定区域与晶体结构研究
  • 批准号:
    41802035
  • 项目类别:
    青年科学基金项目
  • 资助金额:
    12.0万元
  • 批准年份:
    2018
  • 负责人:
    张里
  • 依托单位:
基于数字增强干涉的Phase-OTDR高灵敏度定量测量技术研究