Optimization of 100 Gb/s Short Range Wireless Transceivers under Processing-Energy Constraints

该项目的主题是对工作在60 GHz或120 GHz载波频率、带宽在1到10 GHz之间的无线短程收发信机的新概念进行科学研究。每信息比特的特定处理能量导致功率消耗随着数据速率不成比例地高增长。对于100Gb/S数量级的数据速率，收发信机的功耗将成为一个严重的问题。因此，在该项目中，收发信机将针对最大吞吐量进行优化，特别是在总消耗能量的约束下，即每个信息比特的发送能量和处理能量，从而在给定信息比特率的消耗功率上。为了实现这些目标，我们将研究合适的射频架构和传输方案，以及节能架构，以及它们在真正的跨层方法中的实现。这不可避免地需要基于功耗的设计空间探索。主要的挑战在于如何实现100 Gb/S量级的传输速率，以及如何对信号处理任务进行模拟/数字划分，以支持数据速率但又保持在每信息比特能耗的可接受范围内。因此，该项目的主要目标在于设计创新的射频、混合信号和数字信号处理架构，以实现超高数据速率的高功率效率、带宽效率和实现效率。为了实现这一主要目标，必须研究若干关键问题。这尤其包括实现高调制阶数、多天线传输、分成模拟和数字信号处理、数字调整/切换模拟处理以及高能效硅实现。对于所有概念来说，它们对吞吐量的影响以及它们对总能耗的贡献将是关键参数。因此，能源/功率估算和预算是本项目的进一步重点研究课题。在研究了60 GHz的系统结构和第一阶段数字信号处理的高功耗实现后，第二阶段将在硅上实现关键部件，并将它们的性能与理论分析和模拟确定的行为进行比较。此外，还将研究120 GHz范围(及以上)的功率优化系统架构，这项工作也将用于验证第一阶段开发的基于功耗的设计空间探索方法。

Subject of this project is the scientific investigation of novel concepts for wireless short range transceivers operating at carrier frequencies of 60 GHz or 120 GHz and with a bandwidth between 1 and 10 GHz. A particular processing-energy per information bit leads to a power consumption increasing disproportionally high with the data rate. For data rates in the order of 100 Gb/s the power consumed by the transceiver will become a severe issue. Therefore, in this project transceivers will be optimized for maximum throughput especially under constraints on the total consumed energy, i.e. on transmit- and on processing-energy, per information bit and, thus, on the power consumed for a given information bit rate. In order to achieve the objectives, we will study suitable radio-frequency (RF) architectures and transmission schemes jointly with energy-efficient architectures and their implementation in a real cross layer approach. This inevitably requires a power consumption based design space exploration. Major challenges are in the approaches to achieve transmission rates in the order of 100 Gb/s and in an analog/digital partitioning of the signal processing tasks that supports the data rates but stays within acceptable limits for the consumed energy per information bit.The key objectives of this project thus lie in the design of innovative RF, mixed-signal, and digital signal processing architectures to achieve high power efficiency, bandwidth efficiency and implementation efficiency for ultra-high data rates. To achieve the main objectives a number of key problems has to be researched. This includes, in particular, realization of high modulation orders, many-antenna transmission, partitioning into analog and digital signal processing, digitally adjusted/switched analog processing, and energy efficient silicon implementation. For all concepts their impact on the throughput and their contribution to the total energy consumption will be key parameters. Thus, energy/power estimation and budgeting is a further key research topic of this project. After researching system architectures for 60 GHz and power-efficient implementation of the digital signal processing in the first phase, in the second phase critical components will be implemented on silicon and their performance will be compared to the behavior, which was determined by theoretical analysis and by simulation. Further, power-optimized system architectures for the 120 GHz range (and beyond) will be studied and this work will also be used to validate the power consumption based design space exploration method, developed in the first phase.