Scaling and Performance Potential of Bilayer Graphene Field Effect Transistors for Analog Applications

该项目的重点是研究用于射频模拟应用的双层石墨烯场效应晶体管（gfet）的性能参数和缩放潜力。RF晶体管，例如这里的目标，受益于具有高载流子迁移率和合理带隙的沟道材料。与单层石墨烯相比，在双层石墨烯中，通过在两层之间施加垂直电场可以打开几个100 meV的带隙。在这个项目中，我们将通过制造具有两个独立可控栅极的双栅晶体管来实现这一点。最有可能的是，Bernal堆叠需要实现这一目标，但有一些迹象表明，随机方向也可能起作用。我们打算通过化学气相沉积（CVD）在催化表面（如铜箔和氧化硅上的铜膜）上生长所需的双层石墨烯薄膜。初始沉积实验将在CVD炉中进行，随后将研究等离子体增强CVD技术以降低加工温度。沉积层将被转移到所需的硅衬底上，在那里它们将作为双层gfet的通道材料。微纳米技术将用于制造geft，电子束光刻技术将用于制造各种栅极长度的器件，最小可达20纳米。利用直流参数可以在很大程度上评价晶体管的射频性能潜力。因此，我们将特别研究本征跨导gm、漏极电导gds和本征电压增益AV。基于实验，我们将确定在载流子迁移率和带隙之间权衡的最佳方案。栅极长度变化和温度相关测量将使我们能够研究栅极长度缩放对射频性能的影响，并评估弹道极限下的电输运特性。

The focus of this project is on the investigation of performance parameters and the scaling potential of bilayer graphene field effect transistors (GFETs) for RF analog applications. RF transistors, such as targeted here, benefit from a channel material with high carrier mobility and a reasonable band gap. In contrast to single layer graphene, a band gap of a few 100 meV can be opened in bilayer graphene by applying a vertical electric field across the two layers. In this project, we will achieve this by fabricating double gate transistors with two independently controllable gate electrodes. Most likely, Bernal stacking is required to achieve this goal, but there are some indications that random orientations might also work. We intend to grow the required bilayer graphene films by chemical vapor deposition (CVD) on catalytic surfaces like copper foils and copper films on silicon oxide. Initial deposition experiments will be carried out in a CVD furnace, followed by the investigation of plasma enhanced CVD technology to reduce the processing temperatures. The deposited layers will be transferred onto the desired silicon substrates, where they will serve as the channel material for bilayer GFETs. Micro- and nanotechnologies will be used to fabricate the GEFTs, and electron beam lithography will be employed to fabricate devices with a variety of gate lengths down to 20 nm.The RF performance potential of transistors can be assessed to a great extent with DC parameters. We will therefore study in particular the intrinsic transconductance gm, the drain conductance gds and the intrinsic voltage gain AV. Based on the experiments, we will identify optima in the trade off between carrier mobility and band gap. Gate length variations and temperature dependent measurements will enable us to study the effects of gate length scaling on the RF performance and to assess electric transport properties in the ballistic limit.