CAREER: Enabling Verifiable Computation with Hardware Acceleration

该奖项的部分资金来自《2021年美国救援计划法案》(公法117-2)。随着计算变得越来越普遍，日常生活中受计算直接影响的比例也越来越大。不幸的是，随着对机构信任度的下降，用户发现自己陷入了依赖他们几乎不信任的计算的危险境地。幸运的是，计算机科学中迅速崛起的可验证计算(VC)提供了一个候选的解决方案。不需要用户盲目地相信他们的计算是由其他人正确计算的，用户可以通过检查计算产生的证明来验证是否执行了正确的计算。风险投资的潜在应用越来越多，包括云卸载、金融、不可信芯片制造、区块链压缩和机器学习(ML)。然而，VC目前是不切实际的，因为生成证明的计算代价太高。硬件加速是VC天文数字计算需求的自然解决方案，但不断上升的硬件设计成本使专门硬件的开发变得复杂。该项目通过研究新的硬件架构来加速VC，并通过灵活的硬件设计技术来降低设计成本来解决这两个问题。提供的加速将使更多的VC应用程序变得实用。允许广泛使用VC有益于社会，因为用户将能够单独验证影响他们的计算的完整性。新的设计技术将在一个平易近人的课程中分享，课程的材料将是开源的，并有良好的文档记录。此外，该项目整合了教育努力，如帮助未被充分代表的大学生加强解决问题的技能，以及扩大攻读研究生的人才库。风险投资研究领域的不成熟使硬件加速的开发从多个方面复杂化，该项目旨在解决这些挑战。首先，风投是一个多样化和快速变化的领域，这使得单一的加速器架构不太可能能够支持所有方法。幸运的是，许多方法重用了操作和计算模式，所以这个项目正在创建一个硬件生成器库，它可以作为构建块来构建所需的VC方法。其次，由于VC是如此之新，几乎没有体系结构智慧，也几乎没有关于VC硬件加速的先前工作。生成器的灵活性和可参数化性使扩展的设计空间探索能够高效地发现高效的架构。第三，利用所有的重用机会需要大量的拓扑、操作符和丰富数据类型的组合。该项目正在开发深度组合，以在不牺牲效率的情况下提高重用的抽象级别。为处理新的VC工作负载而开发的创新架构将推动未来的VC应用研究。VC硬件加速器构建块的开源库将帮助启动一个新的研究领域。除了新的课程和推广活动之外，创建一个新的研究领域将有助于扩大和发展硬件设计社区。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

This award is funded in part under the American Rescue Plan Act of 2021 (Public Law 117-2).As computation has become increasingly ubiquitous, so has the fraction of daily life directly impacted by it. Unfortunately, with declining trust in institutions, users find themselves in the perilous position of relying on computations they have little trust in. Fortunately, verifiable computation (VC), a rapidly emerging capability in computer science, provides a candidate solution. Instead of requiring users to blindly trust that their computations are correctly computed by others, users can verify that the correct computation was performed by inspecting a proof produced with the computation. There is a growing list of potential applications for VC including cloud offload, finance, untrusted chip fabrication, blockchain compression, and machine learning (ML). However, VC is currently impractical because generating the proofs is too computationally expensive. Hardware acceleration is a natural solution to VC's astronomical computational demands, but rising hardware-design costs complicate the development of specialized hardware. This project attacks both problems by investigating novel hardware architectures to accelerate VC and agile hardware-design techniques to reduce design costs. The acceleration provided will make many more VC applications practical. Enabling the widespread use of VC benefits society, as users will be able to individually verify the integrity of computations that affect them. The new design techniques will be shared in an approachable course whose materials will be open-sourced and well documented. In addition, the project integrates educational efforts such as helping underrepresented college students strengthen their problem-solving skills as well as broadening the pool of students pursuing graduate study.The immaturity of the VC research area complicates developing hardware acceleration in multiple ways, and this project is intended to solveee these challenges. First, VC is a diverse and rapidly moving field, which makes it unlikely that a single accelerator architecture will be able to support all approaches. Fortunately, many approaches reuse operations and computational patterns, so this project is creating a library of hardware generators that can serve as building blocks to construct the desired VC approaches. Second, since VC is so new, there is little architectural wisdom and nearly no prior work on hardware acceleration for VC. The flexibility and parameterizability of the generators enables expansive design space explorations to productively discover efficient architectures. Third, exploiting all of the opportunities for reuse requires non-trivial compositions of topologies, operators, and rich data types. The project is developing deep composition to raise the abstraction level of reuse without sacrificing efficiency. The innovative architectures developed to handle the novel VC workload will empower future VC application research. The open-source library of building blocks for VC hardware accelerators will help kickstart a new research area. Creating a new research area in addition to the new course and outreach activities, will help broaden and grow the hardware-design community.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.