Dynamically reconfigurable filters for digital signal processing with integrated circuits

提出的项目的目标是为实现数字信号处理的动态可重构滤波器的架构开发优化技术。动态重新配置允许在运行时更改过滤器的属性。这种专用滤波器对于应对信息和通信技术以及先进控制应用中日益复杂的先进应用至关重要。与传统的数字滤波器相比，在运行时调整需求的可能性使得动态可重构滤波器的使用更具优势。除了复杂性的降低，设备成本和功耗的降低也起到了主要作用。这些设计目标可以通过应用计算机辅助优化动态可重构滤波器的自由可编程逻辑，即现场可编程门阵列（FPGA），例如通过共享利用FPGA组件的可能性，该项目涵盖。在这种情况下，通过可重构查找表实现逻辑的动态重构和通过多路复用器实现路由的动态重构都将得到优化。为了进行比较，将应用赛灵思fpga中的部分重构（PR）。我们的目标是能够生成可重构滤波器的优化实现（考虑到功耗、成本和性能的要求），这些可用于数字信号处理的未来应用，并扩展目前的技术水平。解决方案的方法应该适用于fpga，除此之外，还适用于一般的VLSI实现。

The goal of the proposed project is the development of optimization techniques for architectures to realize dynamically reconfigurable filters for digital signal processing. Dynamic reconfiguration allows to change the properties of filters during runtime. Such specialized filters are essential to cope with the rising complexity of advanced applications in information and communication technologies as well as advanced control applications. Having the possibility to adjust the requirements during runtime makes the use of dynamically reconfigurable filters more advantageous in comparison to conventional digital filters. Besides the decrease in complexity, a decrease in device costs and power consumption plays a major role. These design goals can be reached by applying the computer aided optimization of dynamically reconfigurable filters for freely programmable logic i.e. field programmable gate arrays (FPGAs), e.g. by the possibility of shared utilization of FPGA components, covered by the project. In this context both dynamic reconfiguration of logic by reconfigurable look-up tables and dynamic reconfiguration of the routing by multiplexers shall be optimized. Partial reconfiguration (PR) in Xilinx FPGAs will be applied in order to make comparisons. The destinated goal is to be able to generate optimized implementations of reconfigurable filters (concerning the requirements power consumtion, costs and performance) which can be used in future applications of digital signal processing and which extend the state of the art. The approaches to solution should be applicable for FPGAs and besides this for VLSI implementations in general.