Collaborative Research: CSR: Small: Cross-layer learning-based Energy-Efficient and Resilient NoC design for Multicore Systems

芯片上多核的激增标志着以通信为中心而不是以计算为中心的系统的出现。因此，设计低延迟、高带宽、高能效和可靠的片上网络（NoC）被证明是实现未来多核系统性能潜力的最关键挑战之一。然而，由于多核正在促进巨大的集成能力，快速的晶体管扩展导致器件和电路可靠性的稳定下降：不可预测的器件行为将不可预测地增加，并将导致故障（永久性和瞬时性）和硬件故障的显着增加。NoC的后果是巨大的：NoC中的一个故障可能会使整个芯片的工作瘫痪。虽然进行了相当大的努力来解决NoC的可靠性挑战，但大多数当前的解决方案集中在整个NoC抽象内的局部优化（例如，电路、消息和网络层）。这些解决方案往往对整个系统的知识有限，因此在行为上是被动的，做出最坏情况的假设和过度配置，因此，它们引入了显着的功率，面积和性能开销，同时没有完全解决可靠性挑战。本研究项目通过开发一个全面的，合作的，和自适应多层方法，用于从易受故障影响的组件设计可靠的NoC，具有全局优化的功率，性能和成本。为了实现这一研究目标，本项目分为四个相互关联的研究任务。首先，本研究项目进行了全面的研究的基本机制，跨片上网络抽象的可靠性问题的基础。详细分析了NoC抽象和设计权衡的动态交互。其次，该研究项目开发了一种跨层NoC架构，用于基于机器学习的优化的弹性片上通信。第三，该研究项目旨在整合应用层和片外通信，并开发一个整体设计框架，可以自动捕获和适应不同应用的各种计算和通信需求，并优化性能，功耗和可靠性。最后，该项目通过开发周期精确的仿真框架和FPGA原型来评估所设计的框架。该项目将大大推进对NoC与芯片上其他组件（内核、存储器等）之间相互作用的基本理解。以及在未来的大量缺陷纳米技术中性能、功率、可靠性和成本之间的设计权衡。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The proliferation of multiple cores on the chip has signaled the advent of communication-centric, rather than computation-centric systems. Consequently, the design of low latency, high bandwidth, power-efficient, and reliable Network-on-Chips (NoCs) is proving to be one of the most critical challenges to achieving the performance potential of future multicore systems. However, as multicores are facilitating an enormous integration capacity, rapid transistor scaling has led to a steady degradation of the device and circuit reliability: unpredictable device behavior will undeniably increase and will result in a significant increase in faults (both permanent and transient), and hardware failures. The ramifications for the NoC are immense: a single fault in the NoC may paralyze the working of the entire chip. While considerable efforts are undertaken to tackle the reliability challenge of NoCs, most current solutions concentrate on local optimizations within the entire NoC abstractions (e.g., circuit, message, and network layers). These solutions tend to possess limited knowledge of the overall system and are therefore reactive in behavior, making worst-case assumptions and overprovisioning, and as a result, they introduce significant power, area, and performance overheads while not completely solving the reliability challenge.This research project tackles the critical NoC reliability challenge by developing a comprehensive, cooperative, and adaptive multi-layer approach for designing reliable NoCs from fault-susceptible components, with globally-optimized power, performance, and costs. To achieve this research goal, this project is organized into four interrelated research tasks. First, this research project conducts a comprehensive study of the fundamental mechanisms that underlie the reliability issues across NoC abstractions. A detailed analysis of the dynamic interactions of NoC abstractions and design trade-offs. Second, the research project develops a cross-layer NoC architecture for resilient on-chip communication with machine-learning-based optimization. Third, this research project aims to incorporate the application layer and off-chip communications and develops a holistic design framework that can automatically capture and adapt to the various computation and communication requirements of different applications with optimized performance, power, and reliability. Finally, the project evaluates the designed framework by developing a cycle-accurate simulation framework and an FPGA prototype. This project will significantly advance the fundamental understanding of the interplay between the NoC and the rest of the components on the chip (cores, memory, etc.) as well as design tradeoffs between performance, power, reliability, and cost in future massively defective nanometer technologies. The developed NoC framework will benefit future multi-core architectures and computing systems with system-level performance and reliability improvements.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.